Some problems demand hardware that the MCU cannot match. A high-frame-rate vision pipeline, a software-defined radio, a custom motor-control modulator. The answer is HW/SW co-design: partition the algorithm so the FPGA does the inner loop and the MCU does the slow control.
14.1 FPGA + MCU side-by-side
A common pattern: STM32 talks to a Lattice ICE40 or Xilinx Spartan over SPI or memory-mapped FMC. The MCU configures the FPGA at boot, then commands it. The FPGA handles deterministic real-time signals (PWM, decoding, parallel sensor I/O).
14.2 SoC FPGAs
A new class merges them on one die:
- Xilinx Zynq. Dual Cortex-A9 (Zynq-7000) or quad Cortex-A53 + dual Cortex-R5 (Zynq UltraScale+) plus PL fabric. Used in 5G base stations, automotive ADAS, instrumentation.
- Intel Cyclone V SoC, Stratix 10 SoC. ARM cores + FPGA on one die.
- Microsemi PolarFire SoC. RISC-V cores + FPGA. Open ISA.
- Lattice CrossLink-NX. Smaller, edge-AI friendly.
Co-design lets you write the slow plumbing in C on the ARM side and the fast inner kernels in HDL on the FPGA side, with a shared memory map between them.
14.3 Why this matters for security
FPGAs are reconfigurable, so their bitstream is firmware too. Bitstream encryption, signed loading, anti-tamper detection all matter. Hardware accelerators implemented on the FPGA can be custom side-channel-hardened crypto, isolated by gates rather than software policy.