We have walked through the families of hardware attacks: side channels read, fault injection writes, reverse engineering reads the silicon itself, secure boot defends, crypto hardware enforces, JTAG opens windows, supply chain controls lineage, RF security reaches across air, and memory attacks abuse physics. Each has its own literature, its own tools, its own conferences (CHES for side-channel and FI, FDTC for fault injection, SHARCS for reconfigurable, USENIX Security and IEEE S&P for the general field), and its own decade-long arc.
What unifies them is the attacker's mindset: assume the abstraction is a lie, find the layer below, exploit the gap. The cryptographer's mathematics is correct; the engineer's chip is correct; the gap between mathematics and chip is where attacks live. CMOS leaks, registers flip, branches mispredict, refreshes are slow, lasers cut wires, antennas pick up emanations. Every chapter of the curriculum gave you a piece of that gap, and now you can see it.
The defender's mindset is the inverse: assume the attack will be tried, find the gap, close it or detect it. Constant-time code, masking, dual-rail, sensors, redundancy, anti-rollback, tamper meshes, TRR, KPTI. Each defense has a cost in area, power, performance, money, and engineering time, and the design discipline is to spend those costs in the places that matter most.
The capstone in one sentence. Hardware security is the practice of taking every layer of the stack you have learned (transistor, gate, register, instruction, memory, peripheral, protocol, antenna, package, supply chain) and asking, where in this layer does the abstraction leak, and what does it cost to seal it? You now have all the layers and you have all the leak modes. The practice is to mix them, with patience, against a real device, until something gives.