Before we had FPGAs and modern HDL synthesis, designers used programmable logic devices (PLDs) to implement custom logic. The basic structure is an array of AND gates (a "product-term plane") feeding an array of OR gates (a "sum-term plane"), with programmable connections. Whether the AND or OR plane is programmable distinguishes the variants.
| Device | AND array | OR array | Notes |
|---|---|---|---|
| PROM | Fixed (full decoder) | Programmable | Effectively a lookup table. Every input combination has its own AND term. |
| PAL | Programmable | Fixed | Cheap and fast. Each output sums a fixed number of programmable AND terms. |
| PLA | Programmable | Programmable | Most flexible. Each AND term is shareable across multiple outputs. |
A PROM treats logic as a memory: addresses select a row, and the row contents are the function output. A 1024×8 PROM implements any 10-input, 8-output combinational function. Cheap, simple, but wastes silicon for sparse functions.
A PAL trades flexibility for speed and area. It has fixed sums but programmable products, so you can build compact AND-OR logic. The 22V10 (22 inputs, 10 outputs, with optional flip-flops) was a workhorse part for glue logic in PCs throughout the 1980s.
A PLA can share product terms between outputs, which is more compact for functions that overlap.
These have largely been displaced by FPGAs, which are vastly more flexible (every cell is a small programmable mux feeding a flip-flop, with programmable interconnect), and ASICs for high-volume designs. But the concepts of "AND-OR plane" and "programmable interconnect" carry over. A modern FPGA logic cell is essentially a tiny PLA-with-flip-flop.