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section 8 of 114 min read

8. Putting Devices in Circuits: Small-Signal Models

A transistor in a real amplifier is biased at some DC operating point and then asked to amplify a small AC signal superimposed on the DC. To analyze this, we use small-signal models — linearized approximations that capture the AC behavior around the Q-point.

8.1 The big idea

Imagine the transistor's full I-V curve. At any operating point, you can replace the curve locally with a tangent line. The tangent's slope is gmg_m at that point. So as long as the AC swings are small enough that you do not stray far from the tangent, the transistor behaves as a linear device — and we can use all of network analysis (Thevenin, Norton, Bode plots, etc.) on it.

The "small-signal" approximation breaks when you swing too far. Push the input too hard and the output clips. But in a properly designed amplifier, the swings stay in the linear region.

8.2 BJT hybrid-π and h-parameter models

The most common small-signal model for the BJT is the hybrid-π model:

plaintext
   B ─────[r_π]─────┬──────────── C

                  [g_m·v_be]  ← controlled current source

   E ───────────────┴──────────── E
  • rπ=VT/IB=β/gmr_\pi = V_T / I_B = \beta / g_m — base-emitter input resistance.
  • gm=IC/VTg_m = I_C / V_T — transconductance.
  • ror_o (output resistance, models Early effect) — added in parallel with the current source.
  • For high-frequency analysis: add capacitances CπC_\pi (base-emitter) and CμC_\mu (base-collector). We will get to those in Chapter 5.

Equivalent model: h-parameters, which present the BJT as a two-port network with hybrid mixed inputs/outputs:

VBE=hieIB+hreVCEV_{BE} = h_{ie} \cdot I_B + h_{re} \cdot V_{CE} IC=hfeIB+hoeVCEI_C = h_{fe} \cdot I_B + h_{oe} \cdot V_{CE}

with hierπh_{ie} \approx r_\pi, hfeβh_{fe} \approx \beta, hreh_{re} small (typically 10⁻⁴), hoe1/roh_{oe} \approx 1/r_o small. h-parameters are what older textbooks and many exam questions use; they are equivalent to hybrid-π but with different naming.

8.3 FET small-signal model

Simpler than BJT because the gate draws no current:

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   G ──────────┬────[g_m·v_gs]────── D
              (∞)         │          │
                          │         [r_o]
                          │          │
   S ────────────────────┴──────────┴── S

No rπr_\pi — the gate input impedance is essentially infinite. Just the controlled current source and output resistance. Add CgsC_{gs} and CgdC_{gd} for high-frequency.

8.4 Three configurations, side by side

For each transistor and each configuration (CB, CE, CC for BJT; CG, CS, CD for FET), the small-signal model gives specific input impedance, output impedance, voltage gain, and current gain. The standard summary:

ConfigurationAvA_vAiA_iZinZ_{in}ZoutZ_{out}Phase
CE / CSHigh (negative)HighMediumHigh180°
CB / CGHigh (positive)≈1LowHigh
CC / CD≈1 (positive)HighHighLow
  • CE/CS: general-purpose gain stage. The "default" amplifier.
  • CB/CG: high-frequency RF and current amplifier.
  • CC/CD (emitter/source follower): buffer. Use after a high-impedance node to drive a low-impedance load.

8.5 Worked example: a simple CE amplifier

Take the self-bias CE amplifier from section 6, with RC=2.7R_C = 2.7 kΩ, RE=1R_E = 1 kΩ, VCC=12V_{CC} = 12 V, biased at IC=1I_C = 1 mA.

  • gm=IC/VT=1/26=38g_m = I_C/V_T = 1/26 = 38 mS.
  • rπ=β/gm=100/0.0382.6r_\pi = \beta/g_m = 100/0.038 \approx 2.6 kΩ (assuming β=100\beta = 100).
  • Voltage gain (with RER_E bypassed by a capacitor for AC, so AC sees RE=0R_E = 0): Av=gmRC=0.038×2700=103A_v = -g_m R_C = -0.038 \times 2700 = -103. So gain is about 100, with 180° phase inversion.
  • Input impedance: rπr_\pi in parallel with the bias divider — typically a few kΩ.
  • Output impedance: RCR_C in parallel with ror_o — typically a few kΩ.

If we don't bypass RER_E, the gain becomes AvRC/RE=2.7A_v \approx -R_C / R_E = -2.7 — much smaller, but more linear and with higher input impedance and more bandwidth (the RER_E provides local feedback). Whether to bypass or not is a classic design choice.