9. Data Converters: DACs and ADCs // Linear IC Applications // bhaswanth

The bridge between the analog and digital worlds.

9.1 DAC architectures

Weighted-resistor DAC. $n$ binary-weighted resistors ( $R, 2R, 4R, \ldots, 2^{n-1}R$ ), each switched in by one bit. Currents sum at a virtual ground. For an $n$ -bit DAC, resistor values span a $2^{n-1}$ ratio: $2^{15} = 32768$ for 16-bit. Hard to make resistors that precise: a 1% mismatch on the smallest resistor swamps the LSB.

R-2R ladder DAC. Uses only two resistor values, $R$ and $2R$ . The clever switching arrangement produces binary-weighted output currents from the same two values. Small-mismatch trim is easy because all the resistors are close in value.

plaintext

   MSB                                      LSB
    │           │           │            │
    ├──────────●           ●           ●──────●──── V_out
    │           │           │            │      │
   2R          2R          2R           2R     ...
    │           │           │            │
    R           R           R            R
    │           │           │            │
    ●─── R ────●── R ──────●── R ──────●─── ... ── GND
    │
   GND

Bit $k$ either connects its 2R leg to $V_{ref}$ or to ground. The Thevenin equivalent at every node sees $2R$ to the right and $2R$ to the left, so the per-bit contribution to $V_{out}$ is exactly half the next-higher bit's contribution. Binary weighting falls out of the topology, regardless of the specific value of $R$ .

The classic part: DAC0808 (8-bit), AD7541 (12-bit). Modern DACs are much higher resolution (16, 18, 20, even 24 bits) and use segmented R-2R variants or unary thermometer-coded approaches. The AD5791 is a 20-bit precision DAC for instrumentation.

Sigma-delta DAC. Generates a high-frequency 1-bit stream whose density modulates the desired analog output, then low-pass filters it to recover the analog signal. Because the architecture trades amplitude resolution for time resolution, sigma-delta DACs can hit 24-bit performance with very simple analog and very fancy digital. The dominant DAC in modern audio.

9.2 ADC architectures

Flash ADC (parallel comparator). $2^n - 1$ comparators in parallel, each with its threshold set by a tap on a resistor ladder. All comparators fire simultaneously; an encoder converts the thermometer code (a string of 1s up to the threshold, 0s above) to binary.

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Fastest of all ADC architectures (sub-nanosecond conversion). Used in oscilloscopes, software-defined radios, video. Power-hungry: $2^8 - 1 = 255$ comparators for an 8-bit flash; $2^{10} - 1 = 1023$ for 10-bit. Beyond about 10 bits, area and power become prohibitive, so flash is supplemented by other tricks (folding, interpolating, pipelined, two-step) for higher resolution.

The MAX104 is a 1 GSPS 8-bit flash. The AD9213 is a 10 GSPS 12-bit pipelined flash for fast oscilloscopes and electronic warfare receivers.

Successive-approximation register (SAR) ADC. A binary-search algorithm. Start with the MSB: compare the input to $V_{ref}/2$ . If higher, the MSB is 1 and the next comparison is against $3V_{ref}/4$ ; if lower, MSB is 0 and the next comparison is against $V_{ref}/4$ . Repeat for all bits. Takes $n$ clock cycles to produce $n$ bits.

The SAR is the workhorse of microcontroller-integrated ADCs: medium speed (typically 1 to 10 MSPS), low power, modest area (one comparator, one DAC, one register, one control logic). 12-bit and 16-bit SARs are everywhere: AD7980, ADS8881, ADS131M08, MCP3008. Inside every Arduino, every STM32, every ESP32, every nrf52, you find a SAR ADC. Why $n$ clocks for $n$ bits? Because each clock resolves one bit by binary search. Any architecture that resolves multiple bits per clock has to throw multiple comparators at it (flash, pipelined).

Dual-slope (integrating) ADC. Integrate the input for a fixed time $T_1$ , then integrate a known reference of opposite polarity until the integrator returns to zero. The time to do that, $T_2$ , is proportional to the input. Converts $V_{in}/V_{ref} = T_2/T_1$ . Very accurate (the dominant error is the reference, plus integrator linearity). Slow: typically tens of milliseconds per conversion. Immune to mains hum if $T_1$ is set to an integer number of mains cycles, because the integral of a 50/60 Hz sine over an integer cycles is zero. Used in 4½-digit and 6½-digit DMMs (Keithley, Fluke), where the chip is a dedicated dual-slope ADC like the ICL7106 or ICL7136 driving an LCD digit-by-digit.

Sigma-delta ADC. Oversample at much higher than Nyquist with a 1-bit (or low-resolution) front-end loop, then digitally decimate to extract a high-resolution low-rate output.

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The 1-bit modulator's quantization noise is shaped by the integrator's frequency response: noise pushed away from the signal band, into high frequencies. The decimation filter (a CIC followed by FIRs) low-passes and downsamples, extracting only the in-band signal where noise is low. Because the modulator's amplitude resolution is just 1 bit but its time resolution is huge (oversampling ratios of 64, 128, 256 are common), the architecture trades speed for resolution.

The dominant ADC architecture for audio and precision measurement. Every CD, every USB audio interface, every smart speaker has a sigma-delta ADC. The AK4490, AK4499, ESS9038, PCM1794 are audio sigma-delta ADCs. The ADS1262 is a 32-bit sigma-delta (with about 28 effective bits) for ultra-precision instrumentation. The MCP3551 is a 22-bit sigma-delta for cheap precision measurement. The AD7124 is a low-power 24-bit sigma-delta for sensors.

For side-channel power-trace capture in hardware security, fast sigma-delta ADCs like the ADS54J69 (16-bit, 500 MSPS) or pipelined ADCs in ChipWhisperer hardware capture the sub-millivolt signal of interest cleanly through the chip clock harmonics.

9.3 Why each architecture exists (the trade-off triangle)

Speed, resolution, power: pick two.

Need GHz-fast? Flash. (8 to 10 bits maximum at high speed.)
Need 24+ bits? Sigma-delta. (kHz-class speeds at high resolution; faster sigma-deltas exist at lower resolution.)
Need balanced (10-16 bit, MSPS, low power)? SAR. (One comparator, $n$ clock cycles for $n$ bits.)
Need 6½-digit precision and mains-rejection? Dual-slope. (Very slow, fantastic linearity.)
Need pipelined high-speed deep-resolution? Pipelined ADC. (10 to 16 bits at 100 MSPS to 1 GSPS, with latency.)

9.4 Performance metrics

Resolution. Number of bits.
Sample rate. Samples per second (kSPS, MSPS, GSPS).
Linearity. Integral and differential nonlinearity (INL, DNL).
Conversion time. How long for one sample.
SNR. $6.02n + 1.76$ dB for an ideal $n$ -bit ADC. Each bit adds 6 dB.
ENOB (Effective Number of Bits). The actual SNR-derived bit count: $\text{ENOB} = (\text{SNR}_{\text{dB}} - 1.76)/6.02$ . A nominally 16-bit ADC might deliver only 13.5 ENOB at 100 MSPS due to clock jitter, comparator noise, and quantizer nonidealities.
SFDR (Spurious-Free Dynamic Range). Distance in dB from the signal peak to the largest spurious spectral component. Critical for receivers and spectrum analyzers.
THD. Total harmonic distortion, important for audio.

9.5 Anti-aliasing: required, no exceptions

We met this in Chapter 3: every ADC needs a low-pass filter ahead of it that blocks frequencies above $f_s/2$ . The filter's job is to keep out-of-band noise from aliasing into the band of interest. For audio sigma-delta ADCs the anti-aliasing filter is mostly digital (because oversampling pushes the aliases far from the signal band). For SAR and flash ADCs sampling near Nyquist, you need a steep analog filter ahead of the chip.

9.6 Hardware-security tie-ins

ADC quantization as a side channel. Quantization noise is often correlated with internal signal levels, leaking information through nominally noise-only bands.
Voltage-reference attack. Disturb the ADC's reference and every measurement is wrong by a known amount. A common fault-injection target.
Sigma-delta for high-SNR power capture. State-of-the-art side-channel rigs use sigma-delta ADCs for clean capture of nanovolt-level chip-power-rail signals through dB after dB of mains and switching noise.
Flash ADC in attacker scopes. Every fast oscilloscope front-end is a flash or pipelined-flash ADC. The attacker's scope is literally a flash ADC plus cleanup logic plus a memory.