3. 8086 Interfacing: Memory and Peripherals

A bare 8086 by itself does nothing. You need to wire memory and peripherals around it. This is where you really see "microprocessor" vs "microcontroller" diverge.

3.1 Memory interfacing with 74LS138 decoder

To put RAM and ROM in the 8086's 1 MB space, you partition the address space into ranges and map a chip to each. The classic technique: use a 74LS138 3-to-8 decoder to generate eight chip-select signals from three address bits.

                           ┌─────────┐
   A17 ───────────────────┤A   Y0   ├── CS for 0x00000–0x1FFFF (RAM bank 0)
   A18 ───────────────────┤B   Y1   ├── CS for 0x20000–0x3FFFF (RAM bank 1)
   A19 ───────────────────┤C   Y2   ├── ... etc
                          │         │
   M/IO̅ ──────────────────┤G1       │
   AEN ──────────────────┤G2A̅      │
   GND ──────────────────┤G2B̅  Y7  ├── CS for 0xE0000–0xFFFFF (BIOS ROM)
                           └─────────┘
                            74LS138

A17, A18, A19 select one of eight 128 KB regions. M/IO and the AEN gate ensure the decoder only fires on memory cycles when the bus is owned by the CPU. Each Yi line drives a chip-select on an SRAM or ROM. The data bus connects directly; the read/write strobes from the CPU drive the memory chips' control lines. The original IBM PC and PC/AT used exactly this kind of decoded chip-select scheme.

Why M/IO matters. The 8086 has separate memory and I/O address spaces. Memory accesses assert M/IO=1; I/O accesses (IN/OUT) assert M/IO=0. Decoders gate on this so I/O accesses don't accidentally activate memory chip-selects.

3.2 The 8254 programmable interval timer

Three independent 16-bit counters in a single 24-pin chip, each clocked from its own input. Each counter can be programmed to one of six modes:

You program the 8254 by writing a control byte to its command register, then loading the count. The original IBM PC used the 8254 (then called the 8253) for: channel 0 → system tick interrupt (IRQ 0) at 18.2 Hz, channel 1 → DRAM refresh request, channel 2 → speaker tone. Every Linux PC still has an 8254-compatible PIT in its chipset, although modern timekeeping has moved to HPET and the local APIC timer.

3.3 The 8259 programmable interrupt controller

The 8086 has only two interrupt-request pins (NMI and INTR). Real systems have many devices wanting interrupts. The 8259 PIC (Programmable Interrupt Controller) sits between the CPU and devices: it has 8 IRQ inputs (IR0–IR7), prioritizes them, and presents one interrupt request to the CPU's INTR pin, then supplies the vector number when the CPU sends INTA.

                      8086             8259                 Devices
                     ┌────┐           ┌────┐
   IRQ0 ◄────────────┤ IR0│           │ IR0├◄─── 8254 timer
   IRQ1 ◄────────────┤ IR1│           │ IR1├◄─── keyboard controller
                     │    │           │ IR2├◄─── (slave 8259, cascade)
                     │    │           │ ...
                     │INTR├──────────┤INT │
                     │INTA├──────────┤INTA│
                     └────┘           └────┘

The 8259 can be cascaded: one master 8259 drives the CPU's INTR; up to eight slave 8259s connect to the master's IR lines, expanding the system to 64 interrupt sources. The original IBM PC had one 8259 (IRQ 0–7); the PC/AT added a second cascaded on IRQ 2 (giving IRQ 0–15, with IRQ 2 effectively renamed IRQ 9). Modern x86 has the APIC (Advanced Programmable Interrupt Controller) with 24 or more IRQ lines per I/O APIC, plus per-CPU local APICs for inter-processor interrupts — but the kernel still emulates 8259 behavior at boot.

3.4 The 8255 programmable peripheral interface (PPI)

A 40-pin chip giving you three 8-bit parallel I/O ports: A, B, C. Each port can be configured as input or output. Three modes:

• Mode 0: simple I/O. Each port independently in or out.
• Mode 1: strobed (handshaked) I/O. Port C bits act as handshake lines (STB̄, IBF, ACK̄, OBF̄) for ports A and B.
• Mode 2: bidirectional. Port A becomes bidirectional with handshake on Port C.

You configure by writing a control word to the 8255's control register. The 8255 was the workhorse parallel-I/O chip of the 1980s, used to drive printers, switches, LEDs, 7-segment displays, keyboards.

3.5 The 8237 DMA controller

Direct Memory Access lets a peripheral transfer bytes between itself and memory without bothering the CPU per byte. The 8237 has 4 channels, each programmable with source, destination, count, and direction. The CPU sets up the transfer (a few register writes), then signals the device to start, then goes off and does other work. The 8237 raises HOLD to take the bus, executes the transfer cycle by cycle, drops HOLD when done, and fires an IRQ. Original IBM PC used DMA for: floppy disk (channel 2), DRAM refresh (channel 0), spare (channels 1, 3).

Why DMA matters. Without it, copying 1 MB from disk to RAM takes the CPU about 1 million bus cycles of executing IN+MOV. With DMA, the CPU can start the transfer and do other things; the DMA controller does the bus cycles. This is the same idea modern systems use, except the DMA controllers now live inside disk controllers, NICs, GPUs, every smart peripheral.

3.6 The 8251 USART

Universal Synchronous/Asynchronous Receiver/Transmitter. Provides serial RS-232–style communication. You program baud rate, character size, parity, stop bits. The CPU writes a byte to the 8251's data register; the chip serializes it onto the TXD line. Incoming serial bits are deserialized into the receive register; the chip raises an interrupt or sets a status flag. Used in the IBM PC's COM ports, and in any microprocessor system needing async serial.

3.7 ADC and DAC interfacing

ADC0808/0809 is an 8-bit, 8-channel analog-to-digital converter. You select a channel via three address pins (ADD A/B/C), pulse the START line, wait for EOC (End Of Conversion) to assert, then read the 8-bit digital result on the DB0–DB7 lines. Typical interface: tie the ADD/START lines to an 8255 port, read EOC on a status pin or as an interrupt, read the data via another 8255 port.

DAC0808 is an 8-bit current-output digital-to-analog converter. Write 8 bits to it (often via an 8255), get a current proportional to the value out of a current-output pin; pass that through an op-amp transimpedance stage to get a voltage. Used to generate analog control voltages, audio waveforms (early sound cards), or stepper motor drive.

Modern reality. Almost no one wires up a discrete 8255+8254+8259+8237 system today. Everything is integrated into chipsets or microcontrollers. But understanding these chips makes you literate in what's inside every modern SoC: every chipset has a USART (for legacy COM port), a programmable timer, an interrupt controller, a DMA engine, parallel ports. The names changed; the functions did not.