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section 8 of 134 min read

8. ARM Cortex-M: The Modern Successor

The 8051 and PIC dominated the 8-bit world. By the 2010s, ARM Cortex-M chips at similar prices and power had eaten their lunch in new designs. Today, almost every new microcontroller-based product uses a Cortex-M.

8.1 The Cortex-M family

  • Cortex-M0 / M0+: simplest, lowest power, 32-bit RISC. Compete on price/power with 8051. Found in: STM32F0, nRF51, RP2040 (dual M0+).
  • Cortex-M3: more features (hardware divide, bit-banding). The original Cortex-M, in STM32F1, LPC17xx.
  • Cortex-M4: M3 plus DSP instructions plus optional FPU. The workhorse. STM32F4, nRF52, MSP432, MAX32xxx.
  • Cortex-M7: higher performance with caches, double-precision FPU, ~600 MHz capable. STM32F7/H7, NXP i.MX RT.
  • Cortex-M33 / M55: newer, with TrustZone-M (hardware split between secure and non-secure worlds). Used in security-critical IoT.

8.2 What makes Cortex-M different

  • Thumb-2 instruction set: a mix of 16-bit and 32-bit instructions; very dense code. Same ISA across all Cortex-M, so portability is real.
  • NVIC (Nested Vectored Interrupt Controller): built-in to the core; up to 240+ interrupts; per-interrupt priority; tail-chaining (jump from one ISR to another without unwinding the stack).
  • SysTick: a 24-bit countdown timer in the core itself, used by RTOSes for scheduling ticks.
  • Memory-mapped peripherals: all peripheral registers appear in the address space; access them with normal load/store.
  • Bit-banding (M3, M4): each bit of certain RAM/peripheral regions appears as its own 32-bit word, for atomic single-bit access.
  • CMSIS: a vendor-neutral C API for the core, so the same headers work across STM32, nRF, etc.

8.3 Real-world Cortex-M chips

  • STM32 family (STMicroelectronics): vast lineup, hundreds of part numbers from 0.30(STM32G030)to0.30 (STM32G030) to 25 (STM32H7 with Ethernet, USB-HS, large SRAM/Flash). The most popular Cortex-M family.
  • nRF52 / nRF53 (Nordic Semiconductor): Cortex-M4 with integrated Bluetooth Low Energy. In half the BLE devices you own.
  • ESP32 (Espressif): not actually Cortex-M (it uses Tensilica Xtensa cores, sometimes RISC-V for the C3/C6) but spiritually similar — dual-core, integrated Wi-Fi + Bluetooth, very popular in IoT.
  • RP2040 (Raspberry Pi): dual Cortex-M0+ at 133 MHz, 264 KB SRAM, Programmable I/O (PIO) subsystem for synthesizing custom peripherals. The Pi Pico made it famous.
  • NXP LPC, Microchip SAM, Silicon Labs EFM32, Renesas Synergy, Texas Instruments MSP432: all Cortex-M.

8.4 STM32F4 GPIO setup in C

Below is a register-level "blink LED" for STM32F4, showing how Cortex-M peripheral programming actually looks. (Compare to the 8051 SETB P1.0 simplicity — Cortex-M is more powerful but takes a few more lines.)

c
#include "stm32f4xx.h"
 
void delay(volatile uint32_t n) { while (n--); }
 
int main(void) {
    // 1. Enable clock to GPIOA
    RCC->AHB1ENR |= RCC_AHB1ENR_GPIOAEN;
 
    // 2. Set PA5 (Nucleo green LED) as output (mode = 01)
    GPIOA->MODER &= ~(3U << (5 * 2));   // clear bits 10,11
    GPIOA->MODER |=  (1U << (5 * 2));   // set mode = 01
 
    while (1) {
        GPIOA->ODR ^= (1U << 5);        // toggle PA5
        delay(800000);
    }
}

Compared to the 8051 one-liner, this looks fussier — but in exchange you get a 32-bit core at 168 MHz with FPU, USB, Ethernet, dozens of peripherals, megabytes of flash. The complexity of the boilerplate is offset by orders of magnitude more capability.

8.5 ARM Cortex-A: Apple Silicon, smartphones, Pi

Cortex-M is for microcontrollers (no MMU, no Linux, no caches usually). Cortex-A is the cousin used in smartphones, tablets, Raspberry Pi, automotive infotainment, set-top boxes — anywhere you want a real OS. It has MMU, multi-level cache, multiple cores, runs Linux/Android/iOS. The Apple M-series (M1/M2/M3/M4) and Qualcomm Snapdragon are Cortex-A descendants. Different beast from Cortex-M, mentioned only so you can place them in the family.