1. Logic Families: Schools of Thought in Silicon

A logic family is a set of compatible chips manufactured with the same process, sharing voltage levels, drive currents, and switching speeds. Every gate in the family talks to every other gate in the family without translation. Mix two families and you may need a level shifter, a pull-up resistor, or some other glue to bridge them.

Family-as-school analogy. Think of a logic family like a school of philosophy. Each school has its own dialect, its own assumptions, its own "what counts as true." 1980s TTL says "above 2.0 V is a 1, below 0.8 V is a 0, and we run on 5 V." 2020s low-voltage CMOS says "above 0.65 V is a 1, below 0.35 V is a 0, and we run on 1.0 V." Both are right within their own world. Get them in a room together without an interpreter and they talk past each other.

We care about families because choosing one fixes most of the other parameters of a design: power budget, clock speed, noise immunity, and which other chips you can talk to. A good designer knows three or four families fluently and can read the datasheet of any of them to pick the right one for a job.

1.1 Datasheet parameters every family advertises

Every family is characterized by the same dozen numbers. Memorize them and a datasheet stops being mysterious.

Voltage thresholds.

• $V_{IH}$: minimum input voltage that the receiver guarantees to read as a logic 1.
• $V_{IL}$: maximum input voltage that the receiver guarantees to read as a logic 0.
• $V_{OH}$: minimum voltage the driver guarantees to put out for a logic 1 (under specified load current).
• $V_{OL}$: maximum voltage the driver guarantees to put out for a logic 0.

The four thresholds are not independent. For a sane family, the driver outputs more confidently than the receiver demands: $V_{OH} > V_{IH}$ and $V_{OL} < V_{IL}$. The slack between them is the noise margin.

$NM_H = V_{OH} - V_{IH}$ $NM_L = V_{IL} - V_{OL}$

If the driver puts out 4.4 V (typical 74LS $V_{OH}$) and the receiver only needs 2.0 V to call it a 1, you have 2.4 V of high-side noise margin. A 1.5 V spike of ground bounce is harmless. A 3.0 V spike would push the line below $V_{IH}$ and trigger a wrong read. The bigger the noise margin, the more abuse the line can take from crosstalk, ground bounce, EMI, or a careless probe.

Static noise margin geometrically. Plot the gate's transfer curve $V_{out}$ vs $V_{in}$ for two cascaded inverters, one as is, one mirrored. The two curves form a lopsided "butterfly." The biggest square that fits between the wings of the butterfly has side length equal to the static noise margin. SRAM cell stability uses the exact same construction — we will return to it in section 3.

Propagation delay. Time from an input edge crossing 50% to the output edge crossing 50%. Two flavors:

• $t_{PHL}$: propagation delay for a high-to-low output transition.
• $t_{PLH}$: propagation delay for a low-to-high output transition.

Datasheets list both, and they are often unequal because pull-up and pull-down paths are asymmetric. A typical 74LS NAND has $t_{PLH} \approx 11$ ns and $t_{PHL} \approx 7$ ns; a 74HC NAND drops both into the 7-9 ns range; a 74LVC NAND is sub-2 ns.

Power dissipation. Total of static and dynamic.

Static power is the DC current the chip draws when nothing is switching. In TTL it is enormous: the totem-pole output and the multi-emitter transistor are conducting current even at rest. In CMOS it is essentially zero (one transistor of every CMOS pair is always off, breaking the DC path). At deep-submicron CMOS nodes, leakage currents (gate leakage through thin oxides, sub-threshold conduction) bring some static power back, and at 7 nm processes it is half the chip's heat.

Dynamic power dominates in CMOS. Every output transition charges or discharges the load capacitance, dissipating energy $\frac{1}{2}CV^2$ on the rising edge and the same on the falling edge. Multiply by switching frequency $f$ to get power:

$P_{dyn} = C V^2 f$

This single formula has driven 40 years of chip design. Every "low-power" trick in modern silicon is a way of shrinking one of those three factors. Cut $V$ in half (3.3 V to 1.65 V), power drops by a factor of 4. Cut $f$ in half (idle the clock when not needed), power drops by a factor of 2. Cut $C$ (smaller transistors, shorter wires), power drops linearly. The race to lower $V$ and gate $f$ aggressively is why your phone is not a hand warmer.

Fan-out. How many gate inputs one output can drive. Limited by the output driver's current capability and the steady-state current pulled by each input. Standard TTL fan-out is 10. CMOS fan-out is essentially unlimited at DC (CMOS inputs draw no current) but is limited at high speed by capacitive loading: each input adds a few picofarads of gate capacitance, and dynamic power and propagation delay both balloon when too many fan in.

Power-delay product. $P \cdot t_p$. Energy per switching event, in joules. A figure of merit for low-power-fast logic. 1980s TTL was around 50 pJ. 1990s CMOS dropped it to 1 pJ. Modern 7 nm low-voltage CMOS is in the femtojoules per switching event. Half a century of process shrinks compounds.

1.2 The bipolar dynasty: TTL and friends

TTL (Transistor-Transistor Logic) is the family that ate the 1970s and most of the 1980s. The Apollo Guidance Computer used TTL precursors. The Apple I, the original IBM PC, the early Cray machines: TTL inside.

TTL is built from bipolar junction transistors (BJTs) with a clever input stage: a single multi-emitter transistor whose emitters serve as gate inputs. Pull all emitters high and the base-emitter junctions stop conducting; pull any emitter low and one junction conducts; a second-stage transistor inverts and drives the output. The 5 V supply was a deliberate choice: enough headroom for the saturated BJT logic levels with margin, and a friendly number for the 1970s power-supply designs.

Standard TTL (the original 7400 series, 1966) had a propagation delay around 10 ns and dissipated about 10 mW per gate. Useful but power-hungry. The next two decades produced a genealogy of variants, each tuning a knob:

The 74LS series in particular — Low-power Schottky — was the standard glue chip for two decades. If you cracked open a 1980s home computer you saw 74LS00s, 74LS04s, 74LS74s, 74LS161s by the dozens. Even today old industrial controllers are repaired with bags of LS chips bought new from Texas Instruments.

Why Schottky helps. A saturated BJT stores excess charge in its base. To turn off, that charge has to be cleared first, taking nanoseconds. A Schottky diode clamped between collector and base prevents the BJT from going deep into saturation, and the chip switches off in a fraction of the time. Same circuit topology, same transistors, same power; just a metal-semiconductor diode keeping the BJT out of the slow region.

1.3 TTL output structures: totem-pole, open-collector, tri-state

TTL gives you three flavors of output stage. Each maps to a different use case. You will see all three on real datasheets.

Totem-pole. The default. Two transistors stacked: an upper one that pulls the output up to nearly $V_{CC}$, and a lower one that pulls it down to nearly ground. Only one is on at a time. Low impedance in both states, so the output drives capacitive loads quickly and fights off noise. The catch: never tie two totem-pole outputs together. If one driver pulls high while another pulls low, you create a short circuit through the upper transistor of the high driver and the lower transistor of the low driver. The chips heat up, the supply sags, and after a few minutes a transistor lets out the magic blue smoke.

               VCC
                │
               [R]   <-- pull-up resistor (small, 130 Ω-ish)
                │
               [Q1]  <-- "totem-pole" upper transistor
                │
                ├──── output
                │
               [Q2]  <-- lower transistor
                │
               GND

Open-collector (the BJT version) or open-drain (the MOSFET version). The upper transistor is removed. The output can pull low, but cannot pull high on its own; you must add an external pull-up resistor to $V_{CC}$.

                       VCC
                        │
                       [R_pullup]   (external, 1k-10k typical)
                        │
                        ├── output (shared bus line)
                        │
                       [Q]
                        │
                       GND

Why bother? Three reasons.

First, wired-AND. Tie multiple open-collector outputs to the same line. Any one of them can pull the line low. The line is high only if all drivers are off. The pull-up plus the parallel transistors implements an AND function in pure wiring.

Second, level shifting. Drive an open-collector output with one logic family, but tie the pull-up to a different supply. The 5 V chip's open-collector can drive a 12 V relay, or a 3.3 V chip's open-drain can pull up against a 5 V rail with a higher pull-up.

Third, shared buses with arbitration. I²C is the canonical example: every device on the bus has open-drain SDA and SCL. Any device can pull the line low to assert; when no device drives, the pull-ups float the line high. Multiple masters can co-exist because a master that wants to pull high but reads low knows another master is talking and backs off. Wired-OR allowed, in the I²C lingo: the bus is a giant wired-AND of every device's outputs (with negative logic, that means wired-OR of "I want to assert").

The downside: rise time is slow. The pull-up has to charge whatever capacitance the bus has. A 1 kΩ pull-up against 100 pF of bus has $\tau = 100$ ns; faster pull-up resistors waste static current when any device is asserting. This is why I²C maxes out at a few MHz while SPI (totem-pole, dedicated lines) zooms past 100 MHz.

Tri-state. The output has three states: high, low, and high impedance (Hi-Z), where the output disconnects itself electrically from the wire. A separate "output-enable" pin commands the third state.

       enable=1: output drives high or low
       enable=0: output floats (Hi-Z, like the wire is cut)

Tri-state is the bus-arbitration trick that totem-pole made impossible. Multiple drivers connect to one bus; at any given time exactly one has enable asserted while every other sits in Hi-Z. The active driver owns the bus. The CPU's address bus, the memory chip's data bus, every PCI/PCIe segment, and every SD-card or eMMC interface lives on tri-state outputs.

Hardware-security tie-in. Bus contention is a classic fault-injection target. Force two tri-state outputs to drive simultaneously by glitching the enable lines and you can short $V_{CC}$ to ground briefly, droop the supply, and corrupt computations elsewhere on the chip. Some side-channel attacks deliberately enable contention to push a CPU into mis-execution. A "tri-state attack" against a smartcard's internal bus has been demonstrated in academic papers.

1.4 ECL: speed at any price

ECL (Emitter-Coupled Logic) runs BJTs outside their saturation region. Instead of switching a transistor fully on or fully off, ECL biases a differential pair so that current is steered between two transistors but neither saturates. There is no minority-carrier storage to clear, and switching delays drop to picoseconds.

Properties:

• Sub-nanosecond delays. ECL gates ran at 1 ns in the 1980s and below 100 ps by the 1990s.
• Differential signaling. Outputs come in complementary pairs, with logic 0 and 1 expressed as a small voltage difference between the two wires (a few hundred millivolts). Differential signaling rejects common-mode noise.
• Negative supply. Most ECL ran on $-5.2$ V with the logic high near ground. Inverted from TTL conventions.
• Constant current. Because current is just steered between the differential transistors, the chip's current draw is nearly constant regardless of state. Lower switching noise on the supply rails.
• Hot. ECL chips ran ~25 mW per gate at all times. A Cray-1 supercomputer (1976), built almost entirely of ECL, dissipated about 115 kilowatts and used Freon refrigerant pumped through the cabinet to cool it.

ECL ate the supercomputer market for two decades. Cray-1, Cray-2, the Cyber 205, the IBM 3090. Then CMOS process shrinks pushed standard CMOS into the gigahertz range, and CMOS dynamic power scaled with frequency while ECL's static power did not. By 2000 ECL was cornered into niche RF and ATE (automatic test equipment) applications. Today ECL survives in PECL/LVDS variants used for 10/40/100-gigabit Ethernet PHYs, SerDes lanes, and clock distribution networks where sub-picosecond jitter matters.

Why ECL lost. ECL is fast because nothing saturates. But "nothing saturates" means transistors are always conducting, and conducting transistors burn power constantly. CMOS is slow per gate (no current flows except at edges), but the average power per gate is so much lower that you can stack a million CMOS gates and still burn less than a thousand ECL gates. Once CMOS clocks crossed 100 MHz, the speed advantage of ECL no longer outweighed its heat. The Cray engineers cooling their machines with liquid Freon were the canaries; CMOS was the smarter species.

1.5 CMOS: the family that won

CMOS uses a complementary pair: an NMOS transistor (turns on when its gate goes high) plus a PMOS transistor (turns on when its gate goes low). In the static state, exactly one of the pair is on, and there is no DC path from $V_{DD}$ to ground. Static power is essentially zero. Power is dissipated only at switching transitions, when both transistors are momentarily on (the "shoot-through" current) and when output capacitance charges and discharges.

We derived the dynamic-power formula earlier; let us re-derive it carefully because it underpins everything CMOS.

When a CMOS output rises from 0 to $V_{DD}$, the load capacitor $C$ ends up holding charge $Q = CV_{DD}$. Drawing this charge from the supply costs energy $E = QV_{DD} = CV_{DD}^2$. But the cap only ends up storing $\frac{1}{2}CV_{DD}^2$ — the other half was dissipated in the PMOS pull-up resistance during charging. (Resistor + capacitor + step source: half the energy heats the resistor, half ends up in the cap. Pure physics, derivable from $\int i^2 R\,dt$.) When the output falls, the capacitor discharges its $\frac{1}{2}CV_{DD}^2$ through the NMOS, dissipated entirely as heat. Per cycle (one rise plus one fall), total energy dissipated is

$E_{cycle} = \frac{1}{2}CV_{DD}^2 + \frac{1}{2}CV_{DD}^2 = CV_{DD}^2$

Multiply by frequency $f$:

$P_{dyn} = \alpha C V_{DD}^2 f$

where $\alpha$ is the switching activity factor (fraction of cycles where the output actually toggles, typically 0.1 to 0.3 for real circuits). This formula is the most-cited equation in modern chip design. It is why your laptop CPU drops its voltage when idle (DVFS, dynamic voltage and frequency scaling). It is why advanced nodes target ever-lower supply voltages. It is why clock-gating and power-gating dominate the SoC architect's day job.

CMOS family variants:

• CD4000 series. The original 1968 RCA CMOS. Operates from 3 V to 18 V (!), gate delays around 90 ns at 5 V. Slow, but radiation-tolerant and cheap. Still used in noisy industrial environments and educational kits.
• 74C, 74HC, 74HCT. "High-speed CMOS." Pin-compatible with 74LS but lower power. 74HC needs a CMOS-friendly input ($V_{IH} \geq 3.5$ V on a 5 V supply). 74HCT has a TTL-compatible input threshold ($V_{IH} \approx 2.0$ V) for easy mixing with 74LS.
• 74AC, 74ACT, 74AHC, 74AHCT. Faster CMOS. 4 ns delays at 5 V.
• 74LVC, 74AUP, 74AVC. Low-voltage CMOS. 1.65 V to 3.6 V supplies, sub-2 ns delays, 5 V-tolerant inputs on most. The default for modern designs around 3.3 V or 1.8 V.
• 74LVT, 74ALVC. Bus-driver-class low-voltage parts.

1.6 Latch-up: the CMOS pathology

Inside every CMOS chip there are parasitic structures from the layout: pnp and npn transistors that are not supposed to do anything but happen to exist between the n-well, the p-substrate, and the source/drain diffusions. Hooked together, these parasitic transistors form an SCR (silicon-controlled rectifier) — a four-layer device that, once triggered, latches into a low-impedance state and conducts heavily until power is removed.

Trigger latch-up by injecting a transient current into the substrate. The classic trigger is an input voltage that exceeds the supply rails (overshoot above $V_{DD}$ or undershoot below ground). The injected current biases the parasitic SCR into conduction. The chip starts pulling amperes from the supply, the supply may sag (if not current-limited), and a few seconds later the transistors melt down. Cycle the power and the latch-up clears, but the chip may already be damaged.

Mitigations every modern process uses:

• Guard rings. Heavily-doped substrate contacts forming rings around sensitive structures, sinking stray currents before they trigger SCRs.
• Heavy substrate doping (epitaxial process). Lower substrate resistance means injected currents drop too little voltage to forward-bias the parasitic junctions.
• On-die ESD diodes. Clamp every input pin to $V_{DD}$ and ground, intercepting overshoots before they reach the gate.
• Latch-up guard cells in the standard-cell library, automatically inserted by the place-and-route tools.

Hardware-security tie-in. Latch-up is a known fault-injection vector. Inject a beam of high-energy ions or a pulse of laser light into the chip, and you can deliberately trigger latch-up that resets internal state. Smartcards have specific anti-latch-up countermeasures (current monitors, redundant supplies) for exactly this reason.

1.7 Mixing CMOS and TTL

Mixed-family designs are common in retro projects, lab equipment, and any board with both legacy and modern parts.

TTL output → CMOS input. TTL $V_{OH}$ guarantees only ~2.7 V (under load) to ~4.4 V (lightly loaded). 74HC needs $V_{IH} \geq 3.5$ V on a 5 V supply; bare TTL may not deliver. Two fixes:

1. Add a pull-up resistor (typically 1 kΩ to 10 kΩ) from the TTL output to $V_{CC}$. The pull-up bumps the high level to nearly 5 V when the TTL output is high, and the TTL pull-down still wins when low.
2. Use 74HCT instead of 74HC. 74HCT was designed to receive TTL levels: $V_{IH} = 2.0$ V, just like 74LS. Drop-in replacement for 74LS that talks to TTL with no glue.

CMOS output → TTL input. Easier. CMOS swings nearly rail-to-rail, well above $V_{IH}$ and well below $V_{IL}$. The only worry is current: TTL inputs sink ~1.6 mA in the low state, and a small CMOS output (74HC) can sink only ~4 mA. Drive too many TTL inputs and the CMOS output cannot pull low enough.

Mixing supplies (3.3 V CMOS to 5 V TTL). A 3.3 V CMOS high (~3.0 V) is comfortably above 5 V TTL's $V_{IH}$ (2.0 V) but is at risk if the receiving chip is not 3.3-V-friendly on the input. And 5 V TTL output is too high for a non-5-V-tolerant 3.3 V CMOS input — the 4.4 V high will inject current through the input ESD diode into the 3.3 V supply. Two fixes:

1. Use a 5 V-tolerant 3.3 V buffer. 74LVC parts are typically 5 V-tolerant on the input. Read the datasheet.
2. Use a level-translator chip. TXB0108, TXS0102, PCA9306 (for I²C). These have a separate VCCA and VCCB and translate signals between the two voltage domains.

1.8 Low-voltage CMOS and modern multi-rail systems

A modern SoC might have seven internal supply rails: 0.8 V for the CPU core, 1.0 V for the GPU, 1.1 V for the cache, 1.8 V for the DDR4 controller, 1.2 V for the PCIe PHY, 3.3 V for the I/O ring, 5 V for the USB pull-ups. Each rail uses a logic family designed for it. Communication between rails goes through dedicated level shifters.

Why so low? $P = CV^2 f$. At 5 V, switching a 1 pF load at 1 GHz costs $5 \times 10^{-9}$ W per node — manageable for a few nodes, ruinous for ten million. At 1 V the cost drops by a factor of 25. The tradeoff is noise margin: at 1 V supply, the difference between "high" and "low" is 1 V minus a few hundred millivolts of guard band, and a bumpy ground bounce can flip a bit. Modern chips counter this with on-die regulators, decoupling capacitors everywhere, and on-die voltage detectors that pause the clock when the supply droops.

1.9 The comparison table everyone reaches for

Reading this table: TTL is fast for its day but power-hungry and obsolete. ECL beats it on speed but with crippling power. CMOS started slow but caught up while sipping power; today it is the only choice for chips with more than a few thousand gates.

1.10 Real-world chips you will meet

A short tour of chips you can still buy in 2026, where they live, and why:

• 74HC00 (quad NAND, CMOS): glue logic in hobby projects, retrocomputers.
• 74LVC1G86 (single XOR, low-voltage): used in level-shifting and synchronizers.
• MC100EP-series (PECL): clock distribution in 10G/40G Ethernet line cards.
• 74AUP1G125 (single tri-state buffer, ultra-low-power): smartphone GPIO multiplexing.
• CD4017 (decade counter, original CMOS): used in everything from LED chasers to industrial controllers, in continuous production since 1971.
• MC10H189 (ECL, last-of-its-line): test equipment that needs sub-nanosecond timing.

Knowing which family fits which job is the bread and butter of board-level design. Even when an SoC absorbs most of a system, glue chips in the right family handle level shifting, debounce, fan-out, and bus arbitration.