- Falstad transistor-level NAND gate. Open
falstad.com/circuit/. Build a 2-input CMOS NAND from scratch (two NMOS in series, two PMOS in parallel). Confirm the truth table. Try to make it fail by sweeping the input voltage between rails — see where the inverter threshold sits. - Simulate the 6T SRAM cell. Same simulator. Build the 6T cell. Drive WL, BL, BL_bar to read and write. Watch the cross-coupled inverters latch into a state.
- Simulate a DRAM cell with leak. Build a 1T1C cell with a small parallel resistor as the leakage path. Plot the cell voltage over time after a write. See how long until the cell forgets — that is your refresh interval.
- Install GHDL or Verilator. Write the 8-bit LFSR from this chapter. Run a testbench. Confirm the period is 255.
- Buy an iCE40 board. ICEstick or TinyFPGA-BX, $30. Install Yosys + Nextpnr + IceStorm. Build the BCD counter from this chapter. Watch it count on the on-board LEDs.
- Read someone else's HDL. Open the picorv32 RISC-V CPU on GitHub (700 lines of Verilog). See how a real working CPU is structured. Read the testbench. Run the simulation. This is more education than any textbook.
- Try EDA Playground. Browser-based Verilog/VHDL with Vivado or ModelSim simulation. Use templates to learn UVM testbenches.
- Cold-boot attack at home (safe version). Power up a Linux machine, allocate a known pattern in memory, hit reset without powering off. Boot a USB live OS, dump RAM with
memdump. See how much of your pattern survived. Now repeat with a quick power-cycle. The difference is the remanence.
section 8 of 92 min read