3. Programmable Logic: From PLAs to FPGAs

So far our chips have been fixed-function. A 74LS161 is a 4-bit binary counter, period. A 74LS181 is a 4-bit ALU, no more, no less. To build a complex system you wired hundreds of fixed-function chips together. This was the way for thirty years.

Then in the late 1970s came programmable logic: chips whose interconnect could be configured after manufacture. One chip type, many possible behaviors. Today this idea has scaled all the way up to FPGAs containing millions of logic cells.

3.1 PROM as logic: the embryo

Notice that a PROM with $n$ address bits and $m$ output bits implements any combinational function $f: \{0,1\}^n \to \{0,1\}^m$. Just program the PROM so that address $i$ holds $f(i)$. The address pins are the inputs; the data pins are the outputs.

This is the simplest programmable logic device: a lookup table. It is also wasteful — a PROM stores every possible output even when most are 0. But it is universal.

3.2 PLA and PAL: the OR/AND plane idea

A PLA (Programmable Logic Array) is a more efficient structure. Two stages:

1. An AND plane that computes products (terms) of inputs.
2. An OR plane that sums products into outputs.

Both planes are programmable: you choose which inputs feed each AND, and which ANDs feed each OR.

   Inputs ─┬─┬─┬─┬─┬──
           │ │ │ │ │ │
           [   AND plane   ]   (programmable; each row is one product term)
                  │
              product terms
                  │
           [   OR plane    ]   (programmable; each column is one sum)
                  │
                Outputs

A PLA expresses any function in sum-of-products form. We saw the SOP form back in Chapter 4 (K-maps). Convert the K-map into a PLA program: each prime implicant becomes one product term, each output is the OR of the implicants that cover it.

A PAL (Programmable Array Logic) is a PLA with the OR plane fixed (each output gets a hard-wired set of product terms, typically 8). Less flexible than a PLA, but cheaper and faster. The PAL was a 1980s commercial hit; AMD's PAL16L8 became iconic.

PALs and PLAs come in tens of inputs, tens of outputs, and tens of product terms. They are great for state machines, decoders, and address-decoding logic, but they top out around the complexity of a few hundred gates.

3.3 GAL: the erasable PAL

A GAL (Generic Array Logic) is a PAL with EEPROM-programmable interconnect. You can reprogram a GAL many times, unlike fuse-based PALs. Lattice's GAL16V8 was the standard 1990s reprogrammable PLD.

GALs added another wrinkle: each output cell could be configured as combinational, registered (a flip-flop), or tri-state. This made GALs capable of implementing both Mealy and Moore state machines without external chips.

3.4 CPLD: bigger, organized

A CPLD (Complex Programmable Logic Device) is the next size up: many PAL-like blocks connected by a programmable interconnect mesh.

   I/O ── [Macrocell]── [PAL block]──┐
                                     │
   I/O ── [Macrocell]── [PAL block]──┼── [Programmable interconnect matrix]
                                     │
   I/O ── [Macrocell]── [PAL block]──┘

Each "macrocell" includes a flip-flop and tri-state output buffer. The interconnect is a global crossbar (so propagation delays are predictable), making CPLDs deterministic in their timing — important for boot logic and time-critical glue.

CPLDs have three properties that keep them in production:

• Non-volatile. EEPROM- or flash-based; powers up with the configuration ready.
• Predictable timing. Pin-to-pin delays are nearly fixed regardless of design.
• Modest size. Hundreds to thousands of logic cells. Just enough for a state machine, glue logic, address decoder, or boot sequencer.

Common CPLDs: Xilinx CoolRunner-II (still made by AMD), Intel/Altera MAX V, Lattice MachXO. Used as power-management state machines on motherboards, glue logic in embedded devices, DPM (dynamic power-management) controllers.

3.5 FPGA: the big leagues

An FPGA (Field-Programmable Gate Array) is a different beast. Where a CPLD is a few thousand cells of PAL-like logic, an FPGA is millions of logic cells made of small lookup tables (LUTs) and flip-flops, embedded in a sea of programmable interconnect.

An FPGA logic block (often called a CLB or LE depending on vendor) typically contains:

    Inputs ─┬─[ 4-input LUT ]─┬─┬─[ FF ]─┐
            │                 │ │        │
            │                 │ └────────┼── Output
            │                 └──────────┘
            │
    Carry chain ─[ adder logic ]

The 4-input LUT is just a tiny SRAM with 4 address bits and 1 data bit: $2^4 = 16$ memory cells, programmed at configuration time. Apply 4 input signals, get 1 output. The LUT can implement any 4-input function; you just program the 16 SRAM cells with the truth table.

Larger FPGAs use 6-input or 8-input LUTs (Xilinx Versal, Intel Agilex), with optional fracturable structures that compute two smaller functions or one big one.

Around the LUTs are flip-flops (one or more per logic cell), small adders for carry chains (so you can build wide adders without going through the LUT for each carry), and configuration cells that control all the muxes that route signals between blocks.

A modern FPGA also includes hard blocks: dedicated silicon for functions too inefficient to build out of LUTs:

• Block RAM (BRAM). Embedded SRAM blocks (typically 18 Kbit or 36 Kbit each), thousands per FPGA.
• DSP slices. Pipelined multiply-accumulate units for signal processing.
• High-speed transceivers (SerDes). PHYs for 10G, 25G, 56G, 112G Ethernet, PCIe, and other serial protocols.
• Hard processor cores. ARM Cortex-A or RISC-V cores, on the same die. The Xilinx Zynq family pioneered this (an FPGA fabric plus a dual-core ARM); the Intel Stratix 10 has a quad-core Cortex-A53.
• PCIe controllers, DDR controllers, Ethernet MACs.

3.5.1 Configuration and bitstream

When an FPGA powers up, all its SRAM-based configuration cells are zero (or random). A startup process loads the configuration bitstream from external flash: typically a few megabytes for a small FPGA, hundreds of megabytes for a high-end one. The bitstream is a serialized form of the entire chip's configuration: which inputs go to each LUT, which LUTs feed which flip-flops, which signals route to which I/O pins.

After loading, the FPGA "becomes" the digital system you described. Power it down, and the configuration is gone (because the configuration cells are SRAM, volatile). On the next boot, the bitstream is reloaded from flash.

Hardware-security tie-in: bitstream cloning and encryption. Anyone who can read the external flash can copy the bitstream and clone the FPGA's behavior. Vendors counter this with bitstream encryption: the bitstream is AES-encrypted, the FPGA contains a one-time-programmable key (eFuses or BBRAM with a battery), and the FPGA decrypts the bitstream during configuration. Defeating bitstream encryption has been demonstrated by side-channel attacks (DPA on the AES decryptor), fault injection, and probing the on-die SRAM mid-configuration. The Xilinx Virtex-II series was famously broken in 2011; the Xilinx 7-series in 2020. JTAG ports on FPGAs are another attack vector: if not locked, JTAG can read out the configured fabric or inject test bits. Production-grade FPGAs allow JTAG to be permanently disabled by blowing eFuses.

3.5.2 CPLD vs FPGA tradeoffs

A board often has both: a small CPLD that wakes up immediately to manage power sequencing and reset, and an FPGA that boots a few hundred milliseconds later for the heavy lifting.

3.5.3 Vendors

The FPGA market is dominated by three companies:

• Xilinx (since 2022 part of AMD). The largest player. Spartan (low cost), Artix (mid-range), Kintex/Virtex (high end), UltraScale and Versal series.
• Intel (acquired Altera in 2015, spinning back out as a separate business in 2024). Cyclone, Arria, Stratix, Agilex.
• Lattice. Smaller, low-power, popular for IoT. iCE40, ECP5, MachXO. The iCE40 series is famously open-source-toolchain-friendly via Yosys/Nextpnr.

Smaller players: Microchip (acquired Microsemi/Actel; Smartfusion line), GOWIN (Chinese), Achronix.

3.5.4 What FPGAs are used for in 2026

A non-exhaustive tour:

• Network switches and routers. Cisco, Juniper, Arista core boxes are all FPGA-heavy. Custom packet-processing pipelines.
• 5G base stations. Real-time signal processing for OFDM, beamforming, MIMO.
• Software-defined radios. Ettus USRP, HackRF, BladeRF. Radio reception in HDL.
• Bitcoin mining (historical) and crypto-currency mining (some). Outclassed by ASICs for SHA-256 today, but FPGAs remain competitive for newer hashes.
• Machine-learning accelerators. Microsoft Azure's Catapult and Brainwave platforms run inference on Stratix FPGAs. Custom CNNs synthesized to FPGA fabric.
• High-frequency trading. Sub-microsecond order-execution paths; an FPGA reads market data, decides, and emits an order in fewer nanoseconds than software can blink.
• Aerospace and defense. Radiation-hardened FPGAs (Microsemi RTAX, Xilinx Virtex-5QV) on satellites and space probes.
• Prototyping ASICs. Before taping out a chip, designers prototype on FPGAs to validate the RTL.
• Hobby projects. Lattice iCE40 boards (ICEStick, TinyFPGA) at $20-$50.