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curriculum/Digital IC Applications
section 5 of 94 min read

5. Combinational and Sequential MSI Chips

Even with HDL dominating, you should know the classic MSI (medium-scale integration) chips because their idioms persist. Every adder, decoder, multiplexer, counter, and shift register in HDL synthesizes to something that descends from these chip families.

5.1 Adders

We met the half-adder and full-adder in Chapter 4. Real chips:

  • 74LS83 / 74LS283. Cascadable 4-bit adder with carry look-ahead inside.
  • 74F283. Fast Schottky variant.

A modern FPGA does not use these; it uses the dedicated carry chains in its CLB array, which propagate carry at picosecond rates between adjacent cells.

5.2 ALUs

74LS181: a classic 4-bit ALU. Three function-select inputs choose among 16 arithmetic and 16 logic operations. Cascadable to wider widths via carry-in/carry-out and look-ahead.

This was used in the Apollo Guidance Computer's later iterations, the original PDP-11 and PDP-8 lines, and dozens of 1970s minicomputers. A famous student project: build a 4-bit CPU around a 74LS181 and a small register file. The chip is still made for niche industrial uses.

5.3 Decoders, encoders, multiplexers

  • 74LS138: 3-to-8 line decoder. Three address inputs, eight active-low outputs. Used for chip-select generation.
  • 74LS139: dual 2-to-4 decoder.
  • 74LS148: 8-to-3 priority encoder.
  • 74LS151: 8-to-1 multiplexer.
  • 74LS153: dual 4-to-1 multiplexer.
  • 74LS157: quad 2-to-1 multiplexer.
  • 74LS257: quad 2-to-1 mux with tri-state output.

5.4 Comparators

  • 74LS85: 4-bit magnitude comparator (A>B, A=B, A<B). Cascadable.

5.5 Flip-flops

  • 74LS74: dual D flip-flop. The most-used flip-flop chip in history.
  • 74LS76: dual JK flip-flop.
  • 74LS112: dual JK with preset/clear.

5.6 Counters

  • 74LS90: decade counter (mod-10).
  • 74LS92: divide-by-12 counter.
  • 74LS93: 4-bit binary counter.
  • 74LS161: synchronous, presettable, 4-bit binary counter. The workhorse.
  • 74LS163: like 161 but synchronous reset.
  • 74LS162: synchronous decade counter.
  • 74LS192/193: up/down counters.

5.7 Shift registers

  • 74LS164: 8-bit serial-in, parallel-out (SIPO). Used to drive 8 LEDs from a 1-pin SPI source.
  • 74LS165: 8-bit parallel-in, serial-out (PISO). Used to read 8 buttons through 1 SPI input.
  • 74LS166: parallel-in, serial-out with synchronous load.
  • 74LS194: 4-bit universal shift register: hold, shift left, shift right, parallel load.

Used in: LED matrix drivers (chains of 74LS164s on the cheap), industrial output expanders, classic UART receivers (built from a shift register plus state machine before integrated UARTs existed).

5.8 LFSR: the security-relevant shift register

A Linear Feedback Shift Register (LFSR) is a shift register with XOR feedback from selected taps. With well-chosen taps, an nn-bit LFSR cycles through 2n−12^n - 1 states (all possible non-zero states) — a maximum-length sequence, often called an m-sequence or PRBS (pseudorandom binary sequence).

plaintext
     [F1]──[F2]──[F3]──[F4]──[F5]── output
       │                │
       └─── XOR ────────┘
           │
        feedback to F1's input

Properties:

  • Maximum length for taps chosen from a primitive polynomial in GF(2).
  • Statistically random-looking within one period.
  • Fully deterministic. Given the seed and the taps, the sequence is reproducible.
  • Low cost. A 32-bit LFSR is 32 flip-flops and a handful of XORs.

Used in:

  • PRBS test patterns in serial-link testing (PRBS7, PRBS15, PRBS23, PRBS31).
  • Built-in self test (BIST) in chips. The LFSR generates input vectors, a "signature analyzer" (another LFSR) compresses outputs into a checksum.
  • GPS pseudo-random codes (Gold codes are XOR combinations of m-sequences).
  • Stream ciphers. Many old (and broken) ciphers use LFSRs. A pure LFSR is not cryptographically secure — given enough output, you can solve for the taps and seed. Modern stream ciphers combine LFSRs with non-linear filters (Trivium, Grain) or use entirely different constructions (ChaCha20, AES-CTR).
  • Hardware-security PUFs. Some PUF constructions use XOR-LFSR-like challenge-response schemes.
verilog
module lfsr8(
    input  clk,
    input  rst,
    output reg [7:0] q
);
    wire feedback = q[7] ^ q[5] ^ q[4] ^ q[3];   // taps for x^8+x^6+x^5+x^4+1
    always @(posedge clk or posedge rst) begin
        if (rst)
            q <= 8'h01;
        else
            q <= {q[6:0], feedback};
    end
endmodule

This 8-bit LFSR cycles through 255 non-zero states before repeating. Initialize with anything other than zero (zero is a stuck state).