6. Hands-On and Real-World Examples

6.1 The 1980s way: a 4-bit counter on a breadboard

To count from 0 to 9 and display:

1. Crystal oscillator. 1 Hz (or use a 555 timer chain to divide a higher frequency).
2. 74LS90 or 74LS161: the counter.
3. 74LS47: BCD-to-7-segment decoder (for common-anode LEDs).
4. Common-anode 7-segment LED display.
5. Five chips, dozens of wires. About a half-day of work to wire and debug.

6.2 The modern way: same counter on an FPGA

module bcd_counter(
    input        clk,
    input        rst,
    output [3:0] count,
    output [6:0] seg     // 7-segment outputs
);
    reg [3:0] cnt = 0;
    always @(posedge clk or posedge rst) begin
        if (rst)             cnt <= 0;
        else if (cnt == 9)   cnt <= 0;
        else                 cnt <= cnt + 1;
    end
    assign count = cnt;
 
    // 7-segment decoder (common-anode, active-low)
    reg [6:0] s;
    always @* case (cnt)
        4'd0: s = 7'b1000000;
        4'd1: s = 7'b1111001;
        4'd2: s = 7'b0100100;
        4'd3: s = 7'b0110000;
        4'd4: s = 7'b0011001;
        4'd5: s = 7'b0010010;
        4'd6: s = 7'b0000010;
        4'd7: s = 7'b1111000;
        4'd8: s = 7'b0000000;
        4'd9: s = 7'b0010000;
        default: s = 7'b1111111;
    endcase
    assign seg = s;
endmodule

20 lines of HDL, runs on any FPGA. The hard work moves to wiring up a board (programming the FPGA, connecting the LED display) and writing the testbench to verify.

6.3 Inside a digital wristwatch

Every cheap quartz watch has the same architecture:

1. 32.768 kHz crystal oscillator. Why 32.768? Because $2^{15} = 32768$, and 15 successive divide-by-2 stages yield exactly 1 Hz.
2. 15-stage binary counter. One ripple counter or a chain of 74-style flip-flops, divides 32.768 kHz down to 1 Hz.
3. BCD counters for seconds (mod-60), minutes (mod-60), hours (mod-12 or 24).
4. BCD-to-7-segment decoder.
5. LCD driver, multiplexed across digits.
6. Buttons that increment the appropriate stage to set the time.

Total transistor count: a few thousand. Power consumption: a few microamps. A coin cell at 200 mAh runs the watch for years. CMOS is so low power that the rate-limiting factor is the battery's self-discharge, not the watch's load.

6.4 Modern FPGA workflow

1. Write the design in Verilog or VHDL.
2. Run RTL simulation in Vivado XSim, ModelSim, or Verilator. Verify with handwritten testbenches and randomized tests.
3. Synthesize. Tool reports area (LUTs, FFs, BRAMs, DSPs used) and timing.
4. Set timing constraints (XDC for Xilinx, SDC for Intel/Lattice). Specify clock periods and I/O delays.
5. Place and route. Tool places gates physically and routes wires.
6. Run static timing analysis. If timing fails, refactor the RTL: add pipeline stages, change FSM encoding, restructure logic.
7. Generate bitstream.
8. Program FPGA over JTAG.
9. Debug on hardware with ChipScope/SignalTap (in-FPGA logic analyzers that capture signals into BRAM).

6.5 What a cheap modern dev board offers

A $30 Lattice iCE40 stick (UPduino, IceStick) gives you:

• ~5,000 LUTs
• 8-32 KB of block RAM
• A few DSP-ish multiplier blocks
• Open-source toolchain (Yosys + nextpnr + IceStorm)
• 16 MHz on-board oscillator
• USB JTAG programmer

Enough for a small CPU (a RISC-V soft-core fits in ~1500 LUTs), a UART, GPIO, an SPI flash interface, and a custom peripheral. A weekend project.

A $300 Xilinx Artix-7 board (Arty A7) gives you 100 KLUTs, several MB of block RAM, hundreds of DSP slices, and PCIe/Ethernet capabilities. Suitable for serious prototyping.