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section 1 of 1114 min read

1. Linear Wave Shaping

The first half of the chapter takes the simple RC and RL circuits already familiar from Chapter 2 and asks a different question: what happens when their input is a pulse, a square wave, a ramp, or a fast exponential? Sinusoids we already understand from Chapters 2 and 3. The non-sinusoidal inputs are where the digital world meets the analog world, and they are the bread and butter of every circuit between a logic gate and the wider world.

The word linear in "linear wave shaping" means the circuits we are about to look at are made of resistors, capacitors, and inductors only. No diodes, no transistors. No nonlinear behavior. The output is still some weighted sum of the input and its time derivatives or integrals. Section 2 (non-linear wave shaping) will add diodes and transistors, breaking linearity on purpose.

1.1 The RC low-pass: integration in disguise

Place a resistor in series with a capacitor, take the output across the capacitor:

plaintext
   Vin ──[R]──*── Vout
              |
             === C
              |
             GND

We met this circuit in Chapter 2 and computed its frequency response: H(jω)=1/(1+jωRC)H(j\omega) = 1/(1 + j\omega RC), with cutoff frequency fc=1/(2πRC)f_c = 1/(2\pi RC). We also computed its step response: Vout(t)=Vin(1et/RC)V_{out}(t) = V_{in}(1 - e^{-t/RC}), an exponential rise toward the input voltage with time constant τ=RC\tau = RC.

Now we ask the new question: what does this circuit do to a square wave?

The answer depends entirely on how the period TT of the square wave compares to the time constant τ=RC\tau = RC.

Case 1: TRCT \gg RC (square wave is slow compared to the cap's charging time).

The cap has time to fully charge during each high half-cycle and fully discharge during each low half-cycle. The output is essentially an exponential rise to VhighV_{high}, then a flat plateau, then an exponential fall to VlowV_{low}, then a flat valley. It looks almost like the input but with rounded corners.

plaintext
  Vin ┌────────┐         ┌────────┐
      │        │         │        │
      │        │         │        │
   ───┘        └─────────┘        └───
 
  Vout (T >> RC):
       ╱──────╲          ╱──────╲
      ╱        ╲        ╱        ╲
   __╱          ╲______╱          ╲__

The rounding is the RC time constant making itself felt. If you push the period much, much greater than RC, the rounding becomes negligible and you basically get the input back, as if the RC weren't there.

Case 2: TRCT \ll RC (square wave is fast compared to charging time).

This is the interesting case. During the brief high half-cycle, the cap only has time to charge a tiny amount. Because VCV_C is always small compared to VinV_{in}, the voltage across the resistor (which is VinVCV_{in} - V_C) is approximately equal to VinV_{in}. So the current through the resistor is approximately constant: IVin/RI \approx V_{in}/R. A constant current into a capacitor produces a linearly rising voltage: VC=(1/C)Idt=Vint/(RC)V_C = (1/C)\int I\,dt = V_{in} t / (RC).

During the low half-cycle, the input goes to Vin-V_{in} (or whatever the low value is). Same logic, but now the cap discharges linearly downward. The output is therefore a triangular wave at the same frequency as the input, but with much smaller amplitude.

plaintext
  Vin ┌─┐ ┌─┐ ┌─┐ ┌─┐
      │ │ │ │ │ │ │ │
   ───┘ └─┘ └─┘ └─┘ └───
 
  Vout (T << RC):
        ╱╲    ╱╲    ╱╲
       ╱  ╲  ╱  ╲  ╱  ╲
   ───╱    ╲╱    ╲╱    ╲───

The output is the time integral of the input. The RC low-pass filter behaves as an integrator when the input changes much faster than the cap can charge. Run the math more rigorously: if VCVinV_C \ll V_{in}, then IVin/RI \approx V_{in}/R and VC=(1/C)Idt=(1/RC)VindtV_C = (1/C)\int I\,dt = (1/RC)\int V_{in}\,dt. The output is the integral of the input, scaled by 1/RC1/RC.

Bucket-fill analogy. Think of a tap that you're rapidly opening and closing above a bucket with a tiny drain. While the tap is open, water trickles in faster than it drains out, so the level rises a bit. While the tap is closed, the bucket drains slightly, so the level falls a bit. The level traces a slow average of the rapid tap activity. That averaging is integration. Now imagine slowly opening the tap once and leaving it open for a long time: the bucket fills all the way to the brim, then sits there. That is the slow regime where the RC follows the input directly.

The integration is approximate, exact only in the limit VCVinV_C \ll V_{in}. In Chapter 5 we met the op-amp integrator, which uses feedback to enforce V=0V_- = 0 at all times, making the integration exact across a much larger swing. The RC integrator is the cheap, no-power-needed cousin: imperfect but everywhere.

Real-world appearances:

  • Pulse-width-to-voltage converters. A 50% duty cycle PWM through an RC low-pass becomes a DC voltage at half the supply. Cheap analog output from a microcontroller that lacks a true DAC. Every Arduino project that "fakes" an analog output uses this.
  • Anti-aliasing filters before an ADC. Block frequencies above Nyquist, prevent aliasing.
  • Slewing LED drivers. A digital control pin drives an RC into a transistor base; the LED ramps up gently instead of switching abruptly, avoiding visible flicker.
  • Power-on reset circuits. When the chip first powers up, the rail rises faster than the RC can follow; the chip's RESET pin stays low until the cap has charged through a long τ\tau, giving the rest of the system time to settle.

1.2 The RC high-pass: differentiation in disguise

Swap R and C in the previous circuit:

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   Vin ──[C]──*── Vout
              |
             [R]
              |
             GND

This circuit's transfer function is the dual of the low-pass: H(jω)=jωRC/(1+jωRC)H(j\omega) = j\omega RC / (1 + j\omega RC), with cutoff at the same fc=1/(2πRC)f_c = 1/(2\pi RC). It blocks DC and low frequencies, passes high frequencies.

Drive it with a square wave:

Case 1: TRCT \gg RC (slow square compared to RC).

When the input rises by ΔV\Delta V, the cap voltage cannot change instantaneously, so the entire ΔV\Delta V initially appears across the resistor. The output spikes up by ΔV\Delta V. Then the cap charges through R, and the output decays exponentially to zero with time constant τ=RC\tau = RC. When the input falls by ΔV\Delta V, the output spikes negative by ΔV\Delta V, then decays back to zero.

plaintext
  Vin ┌─────────┐           ┌──────
      │         │           │
   ───┘         └───────────┘
 
  Vout (T >> RC):
       ╲              ╲
        ╲              ╲
   ──────╲──────────────╲────────
          ╲              ╲
        positive          negative
        spike             spike at
        at edge           edge, decay

The output looks like a series of sharp positive and negative spikes at each transition of the input, with no signal in between. The RC high-pass behaves as an edge detector and differentiator when TRCT \gg RC. The mathematics: Vout=RCdVin/dtV_{out} = RC \, dV_{in}/dt, the derivative of the input scaled by RCRC.

Case 2: TRCT \ll RC (fast square compared to RC).

The cap doesn't have time to charge between transitions, so the resistor sees nearly the full input swing all the time. The output looks essentially like the input.

The differentiator produces a spike at each rising and falling edge of the input. This is exactly what you want when you need to detect transitions in a digital signal, for example to trigger a one-shot off a button press, or to generate a clock pulse at the start of every byte in a serial protocol.

Banging-the-pipe analogy. Imagine a thin diaphragm separating two halves of a long pipe full of water. Slowly raising the pressure on the input side just slowly bows the diaphragm. But rapidly banging on the input side sends a sharp pressure pulse to the other side. The diaphragm passes only fast changes; it blocks the slowly-built-up pressure. That is what the cap does: it blocks DC, passes the fast edges.

Real-world uses:

  • Edge detectors in digital logic. Chapter 11 will show how a simple AND gate combined with a delay produces a brief pulse on each rising edge, where that delay is often an RC differentiator.
  • AC coupling between amplifier stages. A coupling cap blocks DC bias and passes AC signal between stages.
  • Pulse-shaping in radio receivers. Detect carrier transitions for clock recovery.
  • High-pass audio filters. Remove DC offset from amplifier outputs (which would otherwise burn voice coils).

1.3 Standard input shapes and their responses

Worth memorizing. Every output below derives from solving the RC differential equation with the given input. The reasoning is mechanical once you know what to expect.

InputRC low-pass outputRC high-pass output
Step V0u(t)V_0\,u(t)Exponential rise: V0(1et/τ)V_0(1-e^{-t/\tau})Spike + exponential decay: V0et/τV_0 e^{-t/\tau}
Pulse (width WW)Smaller pulse, smoothed corners (depends on W/τW/\tau)Two spikes (one at each edge)
Square waveTriangle if TτT \ll \tau; replicate if TτT \gg \tauTrain of bipolar spikes if TτT \gg \tau
Ramp ktu(t)kt\,u(t)Lag: rises linearly with delay τ\tau once steadyConstant kτk\tau after transient
Exponential V0eαtV_0 e^{-\alpha t}Depends on ατ\alpha\tau ratio (more next)Modified exponential
SinusoidSame sine, reduced and phase-shifted above fcf_cSame sine, reduced and phase-shifted below fcf_c

The exponential case is worth a moment. If you drive an RC low-pass with Vin(t)=V0eαtV_{in}(t) = V_0 e^{-\alpha t}, you can solve RCdVout/dt+Vout=V0eαtRC\,dV_{out}/dt + V_{out} = V_0 e^{-\alpha t} to get a sum of two exponentials: one at the natural rate 1/τ1/\tau and one at the input rate α\alpha. The relative weights depend on initial conditions. The big lesson: every linear network adds its own time constant onto whatever you put in, and the output is a superposition of input dynamics and circuit dynamics.

1.4 The compensated voltage divider and oscilloscope x10 probes

A pure resistive voltage divider, two resistors in series, attenuates the input by a fixed ratio:

Vout=VinR2R1+R2V_{out} = V_{in} \cdot \frac{R_2}{R_1 + R_2}

Frequency-independent, dead simple. Until parasitic capacitance comes into the picture.

Every real resistor has some shunt capacitance to ground: parasitic capacitance from the PCB trace, capacitance of the next stage's input, even capacitance through the air. Above some frequency, this stray cap shorts out R1R_1, and the divider's attenuation falls off with frequency. The output droops at high frequencies, exactly what you don't want when measuring fast pulse edges.

The fix is elegant: add a deliberate compensation capacitor C1C_1 across R1R_1, sized so that R1C1=R2C2R_1 C_1 = R_2 C_2 where C2C_2 is the (parasitic) capacitance across R2R_2. Now both legs of the divider have the same RC time constant, and the divider behaves as a pure resistive divider at all frequencies, from DC to the edge of light.

plaintext
                C_1
            ┌──╫╫──┐
            │      │
   Vin ─────*──[R1]*──*── Vout
                      |
                 [R2] |
                      |
                =C2   |
                      |
                     GND

The condition R1C1=R2C2R_1 C_1 = R_2 C_2 is the compensation condition. To prove it works, write the impedance of each leg: Z1=R1/(1+jωR1C1)Z_1 = R_1/(1 + j\omega R_1 C_1) for the top leg (resistor and cap in parallel), Z2=R2/(1+jωR2C2)Z_2 = R_2/(1 + j\omega R_2 C_2) for the bottom. The divider ratio is

Z2Z1+Z2=R2/(1+jωR2C2)R1/(1+jωR1C1)+R2/(1+jωR2C2)\frac{Z_2}{Z_1 + Z_2} = \frac{R_2/(1+j\omega R_2 C_2)}{R_1/(1+j\omega R_1 C_1) + R_2/(1+j\omega R_2 C_2)}

If R1C1=R2C2=τR_1 C_1 = R_2 C_2 = \tau, both denominators are equal to (1+jωτ)(1 + j\omega\tau) and they cancel out, leaving

Z2Z1+Z2=R2R1+R2\frac{Z_2}{Z_1 + Z_2} = \frac{R_2}{R_1 + R_2}

Frequency-independent. Pure DC division at all frequencies. Beautiful.

This is exactly how every oscilloscope x10 probe works:

  • Inside the probe tip: a 9 MΩ resistor in parallel with a trim cap (the small adjustable capacitor you tune with a tiny screwdriver).
  • The scope's input: 1 MΩ in parallel with about 15 pF (this is a standard scope input impedance, almost universal).
  • Combined: 9 MΩ + 1 MΩ = 10 MΩ; the divider attenuates by 10 (hence "x10 probe").
  • Goal: tune the trim cap until the trim_cap × 9 MΩ product equals 15 pF × 1 MΩ. Solve: trim_cap should be about 1.67 pF.

When this is right, the probe is frequency-compensated: a square wave on the input shows as a clean square wave on the scope, with no overshoot and no droop.

Most modern scopes have a "probe compensation" output, a square-wave generator at typically 1 kHz. You connect your probe tip to the comp output, look at the displayed square wave, and turn the trim cap on the probe with a tiny tool until the corners are perfectly square. Three failure modes:

plaintext
  Under-compensated:     Over-compensated:        Just right:
  (cap too small)        (cap too big)            (cap exact)
                                                  
   ╱─────╲              ──┬──┬──                  ┌───┐
  ╱       ╲              ╱│  │╲                   │   │
 ╱  droop  ╲           ╱  │  │  ╲                 │   │
                       overshoot                  square!

Always calibrate your probes before serious measurements. An uncompensated x10 probe will lie to you about every fast edge in your circuit, leading to hours of confusion.

1.5 Attenuators and impedance matching

Beyond the scope probe, attenuators are everywhere in test and measurement. A 50 Ω signal generator drives a 50 Ω cable into a 50 Ω input on a network analyzer, and you need to drop the signal by, say, 20 dB without disturbing the impedance match. The Pi attenuator (three resistors arranged in a π\pi shape) and the T attenuator (three resistors arranged in a T) do exactly this: they attenuate by a controlled ratio while presenting 50 Ω at both ports. Standard attenuator pads (3 dB, 6 dB, 10 dB, 20 dB) are sold by the bagful.

In digital design, every transmission line gets some form of termination to prevent reflections (Chapter 9). The simplest is a parallel 50 Ω resistor at the end. Series termination, parallel termination, AC termination using a cap: these are all linear-wave-shaping circuits whose job is to keep the digital edge clean.

1.6 RL circuits and RLC ringing

The RL high-pass and low-pass circuits are exact duals of RC. Time constant is τ=L/R\tau = L/R instead of RCRC. Same math, different hardware. RL filters show up in switch-mode power supplies (where the inductor is the energy-storage element), in RF tuned circuits, and at the inputs of EMI-suppression filters.

The interesting case is RLC ringing. When you drive a series RLC circuit with a step (or a fast edge), the system is second-order: Ld2i/dt2+Rdi/dt+i/C=dVin/dtL\,d^2 i/dt^2 + R\,di/dt + i/C = dV_{in}/dt. Three regimes depending on damping:

  • Overdamped (R2>4L/CR^2 > 4L/C): two real exponentials, slow approach to steady state.
  • Critically damped (R2=4L/CR^2 = 4L/C): fastest non-oscillating response.
  • Underdamped (R2<4L/CR^2 < 4L/C): damped oscillation:

v(t)=V0eσtcos(ωdt+ϕ)v(t) = V_0 e^{-\sigma t} \cos(\omega_d t + \phi)

with σ=R/(2L)\sigma = R/(2L) being the decay rate and ωd=1/(LC)σ2\omega_d = \sqrt{1/(LC) - \sigma^2} being the damped natural frequency.

This ringing is what you see on every fast digital edge. The trace's parasitic inductance, the receiver's input capacitance, and the driver's output resistance form an unintended series RLC. A 1 ns edge into a 5 nH trace and 5 pF load gives you about 1 GHz ringing that takes a few cycles to die.

plaintext
  Ideal step:           Real step with ringing:
  
  ────┐                 ────┐
      │                     │ ╱╲
      │                     │╱  ╲    ╲
      │                     │    ╲    ╲___
   ───┘                  ───┘

Real-world manifestations:

  • Ringing on clock signals in digital systems, which limits maximum clock speed and creates EMI.
  • USB cable ringing from impedance mismatches at connectors.
  • Audio amplifier overshoot on drum hits and percussive transients.
  • Switching-power-supply ringing that radiates as RFI and forces designers to add snubber circuits.

Solutions: termination (a series or parallel resistor matching the line impedance), slow the edges (less bandwidth means less ringing), or deliberate damping (a small resistor in series with the line called a "series-damping resistor"). High-speed PCB design is largely about managing this ringing.

Hardware-security tie-in: EM emanations from clock and data lines are amplified by ringing. A poorly damped digital signal radiates much more than a clean one. TEMPEST analysts look specifically for the resonant frequencies set by trace inductance and gate capacitance, because these are where the leakage is loudest. Defenders add termination and ground planes specifically to kill these resonances.