4. The 555 Timer // Pulse and Digital Circuits // bhaswanth

The 555 is the most-used IC in classroom and industrial electronics. Designed by Hans Camenzind at Signetics in 1971 and released in 1972, the 555 has been in continuous production for over fifty years. It still ships by the millions every year. It is the classroom timer, the hobbyist's first IC, and a workhorse in professional designs where its limitations don't matter.

The genius of the 555 is that it packages everything needed for two of the three multivibrator types (the monostable and the astable) into a single 8-pin chip. Add one capacitor and one or two resistors and you have a precision timer. The internal architecture is simple, easily understood, and worth deriving in detail.

4.1 Internal architecture

rendering diagram...

Inside the package:

Three equal 5 kΩ resistors form a voltage divider, creating reference voltages at 1/3 Vcc and 2/3 Vcc.
Two comparators. Comparator 1 (the "threshold comparator") fires when its input exceeds 2/3 Vcc. Comparator 2 (the "trigger comparator") fires when its input falls below 1/3 Vcc.
An SR flip-flop. Set by Comparator 2, reset by Comparator 1.
A discharge transistor (NPN BJT or NMOS in CMOS variants) whose collector is the "discharge pin" (pin 7). It is on when the flip-flop is reset, off when set. This shorts the timing cap to ground when needed.
An output driver that follows the flip-flop's Q output. Can source or sink up to 200 mA, generous for a small chip and enough to drive an LED or a small relay directly.
A reset input (pin 4) that asynchronously forces the flip-flop reset (output low, discharge on). Tie to Vcc when not used.
A control voltage input (pin 5) that lets you override the 2/3 Vcc reference of comparator 1 from outside, varying the threshold. Tie to a 10 nF cap to ground when not used.

The 8 pins are: 1 GND, 2 trigger, 3 output, 4 reset, 5 control voltage, 6 threshold, 7 discharge, 8 Vcc. Memorize this pinout; you'll use it forever.

4.2 555 in monostable mode

External components: a single resistor R from Vcc to the timing cap, the cap C from that node to ground, and a trigger source on pin 2 (typically through a small cap from a button).

plaintext

               +Vcc
                |
                R
                |
           ┌────*────── pin 6 (threshold)
           |    |
           |    *────── pin 7 (discharge)
           |    |
       ────*    |       
                C
                |
               GND ────  pin 1

Idle state: the flip-flop is reset, output is low, discharge transistor is on, the cap is held at ground. Trigger pin 2 is held high (above 1/3 Vcc) by a pull-up.

When a brief negative pulse arrives at pin 2 (going below 1/3 Vcc), Comparator 2 fires and sets the flip-flop. Output goes high. Discharge transistor turns off, releasing the cap.

Now the cap charges through R toward Vcc:

$V_C(t) = V_{CC} \left(1 - e^{-t/RC}\right)$

When $V_C$ reaches 2/3 Vcc, Comparator 1 fires and resets the flip-flop. Output goes low. Discharge transistor turns on, slamming the cap back to ground. The chip is back in idle, waiting for the next trigger.

The pulse width: solve $V_C(T) = (2/3) V_{CC}$ :

$\frac{2}{3} V_{CC} = V_{CC} \left(1 - e^{-T/RC}\right)$ $e^{-T/RC} = \frac{1}{3}$ $T = RC \ln 3 \approx 1.0986 \, RC$

Conventionally written:

$\boxed{T = 1.1 \, RC}$

The pulse width depends only on R and C, independent of supply voltage (within limits). This is a key feature: the 2/3 and 1/3 thresholds are fractions of Vcc, so they scale together with the supply, leaving the timing equation purely in terms of R and C.

Typical values: R between 1 kΩ and 1 MΩ, C between 100 pF and 1000 µF. Pulse widths from microseconds to hours. With R = 100 kΩ and C = 10 µF: $T = 1.1 \times 10^5 \times 10^{-5} = 1.1$ seconds.

4.3 555 in astable mode

External components: two resistors $R_A$ and $R_B$ , plus capacitor C.

plaintext

           +Vcc
            |
            R_A
            |
            *───── pin 7 (discharge)
            |
            R_B
            |
       ┌────*────── pin 6 (threshold)
       |    |
       |    *────── pin 2 (trigger)  -- threshold and trigger tied
       |    |
       |    C
       |    |
      GND  GND

The cap charges through $R_A + R_B$ toward Vcc until reaching 2/3 Vcc, at which point comparator 1 resets the flip-flop. Discharge transistor turns on, and the cap discharges through $R_B$ alone (the discharge pin pulls the junction of $R_A$ and $R_B$ to ground, so $R_A$ is bypassed). The cap discharges toward 0, but the moment it reaches 1/3 Vcc, comparator 2 sets the flip-flop again. Discharge transistor turns off, cap starts charging again. Forever.

Deriving the timing. The high portion (output high): cap charges from $V_{CC}/3$ to $2V_{CC}/3$ through $R_A + R_B$ , with target $V_{CC}$ .

$V_C(t) = V_{CC} - \left(V_{CC} - \frac{V_{CC}}{3}\right) e^{-t/(R_A+R_B)C} = V_{CC} - \frac{2V_{CC}}{3} e^{-t/(R_A+R_B)C}$

Set $V_C = 2V_{CC}/3$ :

$\frac{2V_{CC}}{3} = V_{CC} - \frac{2V_{CC}}{3} e^{-T_H/(R_A+R_B)C}$ $e^{-T_H/(R_A+R_B)C} = \frac{1}{2}$ $T_H = (R_A + R_B) C \ln 2 \approx 0.693 (R_A + R_B) C$

The low portion (output low): cap discharges from $2V_{CC}/3$ to $V_{CC}/3$ through $R_B$ , with target 0.

$V_C(t) = \frac{2V_{CC}}{3} e^{-t/R_B C}$

Set $V_C = V_{CC}/3$ :

$\frac{V_{CC}}{3} = \frac{2V_{CC}}{3} e^{-T_L/R_B C}$ $e^{-T_L/R_B C} = \frac{1}{2}$ $T_L = R_B C \ln 2 \approx 0.693 \, R_B C$

Total period and frequency:

$T = T_H + T_L = 0.693 \,(R_A + 2R_B) C$ $\boxed{f = \frac{1.443}{(R_A + 2R_B) C}}$

Duty cycle (fraction high):

$D = \frac{T_H}{T_H + T_L} = \frac{R_A + R_B}{R_A + 2R_B}$

Which is always greater than 50%, because the charging path has both resistors but the discharging path has only one. Pure 50% duty cycle is impossible in this topology; the best you can do is make $R_A$ tiny compared to $R_B$ , asymptoting to 50%.

For a true 50% duty cycle, use the 555 astable with a steering diode trick: add a diode from pin 7 to the junction of $R_A$ and $R_B$ , so that during charging only $R_A$ is in the path and during discharging only $R_B$ is. Now $T_H = 0.693 R_A C$ , $T_L = 0.693 R_B C$ , and you can pick $R_A = R_B$ for a true 50% wave.

4.4 555 applications

Just a sample. A book has been written on each:

Blinking LEDs (a classroom rite of passage).
PWM motor speed control. Astable feeding a switching MOSFET, with $R_B$ replaced by a potentiometer to vary the duty cycle.
Audio tone generators. Buzzers, alarms, organ-style toys, theremin-style instruments.
Time-delay relays. Monostable mode driving a relay coil after a fixed delay.
Pulse-position modulation, missing-pulse detectors, frequency dividers, lots of clever things.
Electric fence pulsers. A 555 monostable triggers a high-voltage stage to generate a short, periodic "ouch" pulse that keeps deer out of your garden.
Model rocket timers. A 555 monostable triggers the parachute deploy charge after a calibrated delay.
Cheap LED blinkers and dollar-store flashing toys. Look inside any: there's almost always a 555 (or a cheaper Chinese clone of one).

4.5 555 variants

NE556: dual 555 in one 14-pin package.
TLC555, ICM7555, LMC555: CMOS versions. Work down to 2 V supply, draw far less current (sub-µA in idle), and don't have the bipolar 555's notorious supply-current spike at every output transition.
The original 555 is bipolar (BJT-based) and has a quirky issue: at every output transition, the chip briefly draws a spike of supply current (the totem-pole output stage's two transistors briefly conduct at the same time, a phenomenon called "shoot-through"). This causes ground bounce. A 100 nF decoupling cap right at the chip's Vcc-to-GND pins is mandatory; without it, you'll see misbehavior in adjacent circuits.

4.6 555 as a Schmitt trigger

Tie the threshold (pin 6) and trigger (pin 2) inputs together and use them as the input. With the input below 1/3 Vcc, Comparator 2 sets the flip-flop and output goes high. With the input above 2/3 Vcc, Comparator 1 resets the flip-flop and output goes low. Between 1/3 and 2/3 Vcc, neither comparator fires and the output stays where it was.

This gives a Schmitt trigger with hysteresis of $V_{CC}/3$ , a generous 1.67 V at 5 V supply. Useful when you want serious noise immunity.

4.7 Hardware-security perspectives on the 555

The 555 itself is too slow and too noisy for most security-critical applications, but its quirks are worth noting:

Low-quality random-number source. The exact period of a 555 astable depends on temperature, supply, and the precise threshold of its internal comparators, all of which drift slightly. Sample a 555's output asynchronously with a fast clock and the lower bits do contain some entropy. Not enough for cryptography, but enough for hobbyist applications.
Fault-injection target. The 555's reference voltages (1/3 and 2/3 Vcc) are derived from a simple resistor divider with no protection. A glitch on Vcc directly perturbs the thresholds, changing the timing in a predictable way. Modern secure timers use bandgap-referenced internal voltages instead.
Side-channel emitter. The bipolar 555's shoot-through spike at every output transition radiates strongly. Any device using a 555 in a security-sensitive role leaks its timing relationship via EM.