7. Sampling Gates

A sampling gate is a circuit that passes the input signal through to its output during a precisely controlled "gate" interval and blocks it the rest of the time. Used in sampling oscilloscopes, ADC front-ends, time-division-multiplexed communications, sample-and-hold circuits, and lock-in amplifiers.

7.1 The unidirectional diode gate

The simplest gate: a diode in series, controlled by a gate signal that biases it on or off.

   Vin ──[D]──*── Vout
              |
              R
              |
             GND
   
   The gate signal modulates the diode's bias.
   When biased on: signal passes through.
   When biased off: diode blocks the signal.

Limitations: passes only one polarity; the gate signal leaks through (a phenomenon called pedestal); the diode's forward drop attenuates the signal.

7.2 The bidirectional and four-diode bridge gates

A four-diode bridge is much better. Picture four diodes arranged in a square (like a bridge rectifier). The input enters one diagonal, the output exits the other. Two control voltages bias the bridge: when both are present at appropriate polarity, all four diodes conduct, and the bridge becomes a low-resistance link from input to output. When the control voltages reverse, all four diodes are off, and the bridge is a near-open. The symmetry cancels the gate signal's leakage to the output, dramatically reducing pedestal.

   Vin ──*──*──── Vout
         |  |
        D1 D2
         |  |
         *──*  ── (control voltages)
         |  |
        D3 D4
         |  |
        GND GND  
   
   (Schematic is approximate; standard 4-diode bridge layout)

Six-diode and more elaborate bridges achieve even less leakage, used in precision instruments.

7.3 Transistor sampling gates

A FET (especially a MOSFET) makes an excellent sampling gate: low on-resistance, very high off-resistance, no DC offset (unlike a diode). Bipolar transistors can also work, with a bit more complexity.

The on-resistance of a MOSFET acting as a switch is the $R_{DS(on)}$ of the device, typically a few ohms for small-signal MOSFETs and milliohms for power devices. The off-resistance is essentially infinite (gigohms). This makes the FET nearly ideal, and it's what's inside every analog multiplexer chip (CD4051, ADG7xx series, etc.).

7.4 Sample-and-hold

A sampling gate followed by a hold capacitor (the sample-and-hold (S/H)) captures the input value at the gate moment and holds it. Every ADC has an S/H at its front end so the input stays steady during the conversion (which can take microseconds).

   Vin ──[FET switch]──*── output (held)
                       |
                       C (hold capacitor)
                       |
                      GND
                      
   When switch is closed: output tracks input ("track" or "sample" mode).
   When switch opens: cap holds whatever value it had ("hold" mode).

Critical S/H parameters:

• Acquisition time. How long it takes to settle to the new input value when the switch closes.
• Aperture jitter. Variability in the exact moment of sampling (limits ADC effective bits at high frequency).
• Droop rate. How fast the held voltage decays due to leakage. Set by the cap value and the leakage of the buffer's input.
• Pedestal. DC offset caused by switch capacitive coupling.

7.5 Where sampling gates appear

• Sampling oscilloscopes for sub-nanosecond timing. Use equivalent-time sampling: rather than sampling fast in real time, take one sample per cycle of a periodic signal at progressively shifted times, building up a high-resolution waveform from many cycles. This is how scopes hit 100 GHz bandwidth: they don't, in real time; they reconstruct it.
• Time-division multiplexing. Multiple signals share a channel by time slots; samplers select the right slot at each end.
• ADCs. Front-end S/H, as just described.
• Boxcar averagers. Repeated sampling at the same point of a periodic signal, averaged across many repetitions for noise suppression. Used in physics labs and also in hardware-security side-channel measurements (averaging power traces across many encryption operations to reduce noise).
• Switched-capacitor filters. A whole class of filter using only switches and caps, no resistors; relies on sampling gates for the switching.
• Chopper-stabilized op-amps. Sample the input rapidly to remove DC drift.

7.6 Hardware-security perspectives

Sampling gates and S/H are the workhorses of side-channel measurement. An attacker measuring a chip's power consumption or EM radiation needs to capture a brief transient signal at exactly the right moment relative to the chip's internal events. The S/H in their measurement front-end (or the sampling circuit in their high-speed scope) has to be:

• Triggered with picosecond accuracy relative to the chip's clock.
• Wide-bandwidth (to catch fast switching transients).
• Low-noise (each measurement contributes random error).

Counter-attacks include clock jitter (randomizing the chip's clock to disrupt the attacker's sampling alignment) and dummy operations (inserting noise events that confuse the sample-aligned correlation analysis).