6. Logic Families

A logic family is a set of compatible gates manufactured with a common process, sharing voltage levels, current capabilities, and switching characteristics. Mixing devices from different families is possible but requires interfacing (level shifters or careful voltage choices).

The history of digital logic is a march from slow-and-power-hungry to fast-and-low-power, driven by progress in semiconductor technology. Each family represents a tradeoff among speed, power, voltage, integration density, and cost.

6.1 The parameters that matter

Every logic family is characterized by a few key numbers:

• Propagation delay $t_p$. Time from a 50%-input crossing to the corresponding 50%-output crossing. Limits the maximum clock frequency. Different for low-to-high ($t_{PLH}$) and high-to-low ($t_{PHL}$).
• Power dissipation. Static (when the gate is sitting in a steady state) plus dynamic (charging/discharging load capacitances during transitions).
• Voltage levels: $V_{IL}$ (max input voltage still recognized as low), $V_{IH}$ (min input still recognized as high), $V_{OL}$ (max output voltage in the low state), $V_{OH}$ (min output in the high state).
• Noise margins. $NM_L = V_{IL} - V_{OL}$ (low-side noise margin), $NM_H = V_{OH} - V_{IH}$ (high-side noise margin). How much voltage noise the gate can tolerate without flipping incorrectly.
• Fan-out. Maximum number of input loads that one output can drive while still meeting voltage and timing specs. Driven by the output's current-driving capability vs each input's loading.
• Power-delay product. Energy per switching event (typically picojoules). The fundamental "figure of merit" for a logic family, where lower is better.
• Operating temperature range. Commercial (0 to 70 °C), industrial (-40 to 85 °C), military (-55 to 125 °C).

6.2 RTL: Resistor-Transistor Logic (1960s)

The earliest IC logic, used in the Apollo Guidance Computer. Inputs go through resistors into the bases of transistors; the transistor outputs are wired-AND'd. Crude but functional. Slow (~ 100 ns delay), poor noise margins, mostly historical now.

6.3 DTL: Diode-Transistor Logic (mid-1960s)

Inputs go through diodes (which form an AND or OR), then drive a transistor. Better noise margins than RTL, but slower than what came next.

   Inputs ──[D1]──*── [R] ── base of NPN  ── output
          ──[D2]──│
          ──[D3]──│
                  
  Diodes form an AND of the inputs (output high only if all inputs high).
  Transistor inverts and drives output.

DTL was the immediate predecessor to TTL and shares the AND-then-invert structure, just with input diodes instead of multi-emitter transistors.

6.4 TTL: Transistor-Transistor Logic (1970s-1980s)

The big innovation in TTL was the multi-emitter transistor at the input: a single transistor with multiple emitters acting as multiple "input diodes" at no extra silicon cost. This made TTL fast and cheap.

   Inputs ──*── (multiple emitters of input transistor)
          ──*
          ──*
              │ (input transistor, base biased to Vcc through R)
              │
              ▾ (collector drives the rest of the circuit)
              ...
              
  Output stage: "totem-pole": two transistors stacked, one pulling
  output high, the other pulling it low. Active in both directions.

The 7400 series (introduced in 1966 by Texas Instruments) became the de facto standard for digital logic for two decades. Variants:

• 74: standard, ~10 ns propagation delay, ~10 mW per gate.
• 74L: low power, ~33 ns delay, 1 mW per gate. Slow but cool.
• 74H: high speed, ~6 ns delay, 22 mW per gate. Fast but hot.
• 74S (Schottky): ~3 ns delay, 19 mW per gate. The Schottky-clamped trick prevents deep saturation, eliminating storage time. Major speedup.
• 74LS (Low-power Schottky): ~10 ns delay, 2 mW per gate. The workhorse for decades; "the 74LS series" is what many engineers think of when they hear "TTL."
• 74AS, 74F: advanced/fast, sub-3 ns delay.

TTL output structures:

• Totem-pole. The standard output: an upper transistor pulls the output high through a resistor (or actively), a lower transistor pulls it low. Active in both directions. Cannot be wire-OR'd because two outputs disagreeing would short-circuit each other.
• Open-collector. Only the lower (pull-down) transistor is present. The output can be connected to a pull-up resistor externally. Multiple open-collector outputs can be tied together: the wire is high only if all outputs are high, a wired-AND. Used for I²C, interrupt lines, status flags.
• Tri-state (3-state). Output can be high, low, or high-impedance (effectively disconnected). Essential for buses with multiple devices sharing the same wires: only one device drives at a time, the rest are tri-stated.

TTL voltage levels (5 V supply):

• $V_{OH}$ = 2.4 V (min), $V_{IH}$ = 2.0 V (min)
• $V_{OL}$ = 0.4 V (max), $V_{IL}$ = 0.8 V (max)
• Noise margin: 0.4 V on each side.

Power dissipation: ~ 10 mW/gate static, plus dynamic. A board with hundreds of gates dissipated watts continuously, requiring decent power supplies and heatsinking.

6.5 ECL: Emitter-Coupled Logic

ECL keeps the BJTs in the active region rather than letting them saturate. This eliminates storage time entirely, making ECL the fastest logic family around. Sub-nanosecond delays were routine in the 1970s-80s.

The price: every gate has DC current always flowing. ECL is power-hungry and runs hot. A 1976 Cray-1 supercomputer, built almost entirely from ECL, dissipated 115 kW and required liquid Freon cooling.

ECL voltage levels are unusual: typically running from $-5.2$ V to ground, with logic levels at about $-1.8$ V (low) and $-0.9$ V (high). The differential nature (each gate has both true and complement outputs available) means ECL is inherently good at driving transmission lines and resistant to common-mode noise.

ECL is largely obsolete now (CMOS is faster and cooler), but its descendants live on:

• PECL (Positive ECL): same logic shifted to positive supplies.
• LVDS, LVPECL, CML (Current-Mode Logic): differential signaling derived from ECL principles, used in every high-speed serial link (USB 3, PCIe, HDMI, DisplayPort, 10G Ethernet, SATA).

6.6 CMOS: the modern dominant family

CMOS uses complementary NMOS + PMOS pairs. Every gate has an NMOS pull-down network and a PMOS pull-up network designed so that exactly one is conducting at any steady state. The other is fully off.

     Vcc
      |
   ┌──*──┐
   |     |
   PMOS  PMOS    (pull-up network)
   |     |
   *─────* ── Output
   |     |
   NMOS  NMOS    (pull-down network)
   |     |
   ───┬───
      |
     GND

Key properties of CMOS:

• Static power: essentially zero. Only one transistor in any pair is on at a time, so no DC current path from Vcc to GND. The only static current is leakage (subthreshold conduction, gate leakage), which is usually picoamps to nanoamps.
• Dynamic power. Energy per switching event is $E = CV^2$ (where $C$ is the load capacitance and $V$ the supply voltage). Power at switching frequency $f$:

$P = \alpha C V^2 f$

where $\alpha$ is the switching activity factor (fraction of clocks during which the gate actually transitions). The $V^2$ scaling is the reason every modern chip aggressively scales down its supply voltage. Halving the supply quarters the dynamic power.

• Voltage flexibility. Original 4000-series CMOS works from 3 to 15 V; modern CMOS runs at sub-1 V cores and 1.8-3.3 V I/O.
• High noise margins. CMOS gates have sharp transfer curves, and noise margins are often 30-40% of Vcc.
• High input impedance. MOSFET gates draw zero DC current, so fan-out is essentially unlimited, limited only by capacitive loading and timing.

CMOS family variants:

• 4000 series. Original (1968), slow but operates 3-15 V. Still made for ultra-low-power and high-voltage industrial applications.
• 74HC. "High-speed CMOS," pin-compatible with 74LS but lower power. 5 V supply, ~10 ns delays, microwatts of static power. Replaced 74LS in most new designs by the 1990s.
• 74HCT. Like 74HC but with TTL-compatible input thresholds, useful when interfacing to existing TTL designs.
• 74AC, 74ACT, 74AHCT. Faster CMOS variants, ~5 ns delays.
• 74LVC. Low-voltage CMOS for 1.8-3.3 V systems.
• 74AUP. Ultra-low-power CMOS for battery-operated devices.

Power-delay product for modern CMOS at low voltage is in the femto-joule range, millions of times better than 1970s TTL.

6.7 Comparison table

6.8 Hardware-security perspectives on logic families

• Power-analysis side channel. Static-CMOS gates dissipate energy during transitions proportional to the data being processed. A gate that flips its output draws charge from Vcc; one that doesn't, draws nothing. By measuring the chip's total supply current with high time resolution, an attacker can correlate current spikes with bit transitions and recover internal data, including encryption keys. Differential Power Analysis (DPA) does exactly this.
• EM emanations. Each transition radiates a brief EM pulse. The spectrum shows clock harmonics and data-dependent components. Tempest analysts collect this with antennas; defenders use balanced-output signaling (similar to LVDS) to cancel the radiated component.
• Glitch attacks on setup/hold. A flip-flop has a setup time (data must be stable before the clock edge) and hold time (data must remain stable after). Push a fast pulse onto a data line at exactly the wrong moment and the flip-flop captures the wrong value. Attackers use this to skip critical instructions (like authentication checks) or corrupt sensitive data. Older, slower logic families are more forgiving of timing violations; modern, fast logic is more vulnerable.
• Logic-family identification by chip decapping. When attackers decap a chip and look at the silicon, the layout patterns reveal which family the designer used. CMOS has distinctive complementary structures; ECL's differential layout is unmistakable. This informs attack strategy.
• Asynchronous and dual-rail logic as countermeasures. In dual-rail logic, every signal is represented by two wires that always switch in opposite directions, so the total switching activity is constant regardless of the data. This is one of the most effective countermeasures against power analysis but doubles the area and power.