1. From Vacuum Tubes to a Trillion Transistors

1.1 SSI, MSI, LSI, VLSI, ULSI

The integration density of an IC is measured in roughly how many gates fit on one chip, and the industry has used a shorthand for the decades:

The boundaries are arbitrary marketing labels. Engineers today say "VLSI design" to mean any serious chip-design work, regardless of transistor count, just as people still say they "dial" a phone number even though no rotary dial is involved. What matters is that we are talking about chips with so many transistors that nobody can route them by hand, and the entire production machinery, EDA software, photomasks, fabs, packaging, has scaled to match.

1.2 Moore's Law: an empirical observation that became a self-fulfilling roadmap

In 1965 Gordon Moore, then at Fairchild, plotted the number of components per IC on a log scale and noticed it was a clean exponential. He predicted, in a tossed-off magazine article, that the number would double roughly every year. By 1975 he revised this to "every two years," which is the form people remember as Moore's Law.

Moore's Law is not a law of physics. It is an industry roadmap that became self-fulfilling because every fab, every EDA company, every IP supplier, and every customer planned around it. If TSMC said "we will have a node with 2x density in two years," every chip designer planned a product to ship on that node, every tool vendor wrote tools for that node, every memory supplier scheduled silicon to feed those products, and so on. When everyone is rowing in the same direction, the boat moves.

The doubling did not come from any one trick. Each generation came from a careful blend of:

• Smaller transistors (lithography improvements).
• New transistor structures (planar to FinFET to gate-all-around).
• New materials (high-k dielectrics, copper interconnect, strained silicon, low-k dielectrics, cobalt fill).
• More metal layers and better routing.
• Bigger chip area (within reticle limits) and better yield.

Real-world frame. From 1971 (Intel 4004, 2,300 transistors) to 2024 (Apple M4 Max, ~28 billion), transistor count doubled about 24 times. That is a factor of 16 million increase in 53 years. No other engineering discipline has matched this.

1.3 The end of Dennard scaling

Robert Dennard at IBM described in 1974 how to shrink transistors so that everything got better at once. Shrink linear dimensions by a factor $S$, shrink the voltage by the same factor $S$, and:

• Capacitance per transistor falls as $1/S$.
• Current per transistor stays roughly proportional to $V/L$, scaling carefully.
• Switching delay $\tau \propto CV/I$ falls as $1/S$, so the chip gets faster.
• Power per transistor $P \propto CV^2 f$ falls as $1/S^2$, while density rises by $S^2$, so power per area stays constant.

This was the dream: shrink, get faster, denser, lower power, all at once. It worked for thirty years.

Around 2005 the trick broke. The reason is that the threshold voltage $V_{th}$ of a MOSFET cannot be scaled arbitrarily low. Subthreshold leakage current depends exponentially on $V_{th}/(kT/q)$, and at room temperature $kT/q \approx 26$ mV. Push $V_{th}$ much below ~300 mV and leakage explodes.

With $V_{th}$ stuck, you cannot drop $V_{DD}$ much further (you need headroom $V_{DD} - V_{th}$ to keep transistors on). With $V_{DD}$ stuck, $CV^2 f$ no longer falls per generation. Power density, the heat per square millimeter, stops falling. And once you cannot get rid of heat, you cannot crank the clock. This is why your CPU has been stuck near 5 GHz since 2005.

The industry's response has been to scale by adding cores, by adding specialized accelerators (GPU, NPU, video, crypto, ISP), by improving cache and interconnect, and by using power gating to keep huge swathes of the chip dark when not in use. The era of "free lunches from process scaling" is over. The era of "architectural cleverness to extract value from shrinking" is here.

1.4 Why this matters for security

Two things follow from Moore's Law breaking that are deeply relevant to hardware security. First, the leakage that broke Dennard scaling is the same leakage that is exploited by static side channels, where simply measuring the standby current of a chip can reveal the state of certain SRAM cells. Second, the move to architectural cleverness means more side-channel surface, more shared resources between cores (caches, branch predictors, ring buses) which became the launching pads for Spectre, Meltdown, RowHammer, MDS, and dozens of other attacks. Hardware did not get less secure on purpose. It got less secure because the easy speedups dried up and engineers started picking up the harder, riskier ones.