A modern chip from idea to product:
- Architecture: spec a new SoC. Block diagrams, perf/power/area budgets. ~6 months.
- RTL design: SystemVerilog written by tens to hundreds of engineers. 12 to 18 months.
- Verification: testbenches, formal proofs, emulation, in parallel with design. Often a larger effort than design itself.
- Synthesis: RTL to gate-level netlist (Synopsys Design Compiler, Cadence Genus).
- Floorplan: blocks placed within the die outline; power grid drawn.
- Place-and-route at cell level (Innovus, ICC2, Aprisa). Days to weeks of compute.
- Sign-off: STA, power, EM, IR drop, DRC, LVS, antenna, all green at multiple PVT corners. 2 to 3 months of iteration.
- Tape-out: GDS-II/OASIS to the foundry.
- Mask making: 80+ masks, 100M for N5/N3.
- Wafer fab: 3 to 4 months in the cleanroom.
- Wafer probe, dice, package, final test, burn-in.
- Bring-up: silicon back at the design team, real software runs on it. Some bug or speed path is always found and worked around in firmware/ECO.
- Qualification + ramp + ship.
Total time, concept to shipping: 2 to 4 years. Cost for a leading-edge SoC: 1B. This is why only a handful of companies play at the leading edge.