12. Memory Design

Memories are one of the most-engineered structures on a modern chip. SRAM occupies 30 to 50 percent of CPU die area in the form of caches. DRAM is fabricated in dedicated processes and packaged separately, but the bit cell is so important that we must understand it.

12.1 SRAM 6T cell

The classic six-transistor SRAM cell:

        WL (word line)
           |
           |
    BL ──[N1]──*── ─[N2]── BL_bar
                |       |
              [INV1]  [INV2]
                |       |
               GND     GND  (and V_DD on top of inverters)
                \________/
                 cross-coupled

Two cross-coupled CMOS inverters store a bit. Two access NMOS transistors (N1, N2) connect the storage nodes to the bit lines BL and BL_bar when the word line WL is high. Read by precharging both bit lines high and pulsing WL: whichever side stores 0 pulls its bit line down slightly; a sense amplifier detects the difference. Write by driving BL and BL_bar to the desired values and pulsing WL with enough strength to overpower the cell.

The 6T SRAM cell is the smallest device on a modern chip and the area metric all other cells are scaled by. A single CPU cache may have a billion of these cells.

12.2 8T SRAM (low-power variant)

For low-power and ultra-low-voltage SRAM, an 8T cell separates the read and write paths. Two extra NMOS form a dedicated read port that does not disturb the storage nodes. Used in mobile chips (Apple A-series, Qualcomm Snapdragon) where minimum voltage matters for battery life.

12.3 DRAM 1T1C

A DRAM cell is one transistor and one capacitor:

   BL
    |
   [N1]─── WL
    |
    *
    |
   [Cs]
    |
   GND

Charge on $C_s$ encodes the bit. Read by pulsing WL and sensing the tiny voltage shift on the bit line (the bit-line cap is much larger than $C_s$, so the swing is small, ~100 mV). Read is destructive; the sense amplifier must rewrite the cell. The capacitor leaks; cells must be refreshed every few milliseconds.

DRAM is not built in CMOS logic processes. It uses a specialized process with deep-trench or stacked capacitors to maximize $C_s$. This is why DRAM is fabricated by Samsung, SK Hynix, Micron in dedicated fabs.

12.4 Sense amplifiers

A sense amplifier is a fast latch that resolves a small differential voltage on a bit line into a full-rail digital output. The classic design is two cross-coupled inverters with a precharge transistor; the sense amp is "kicked" by a small initial difference and rapidly amplifies it.

12.5 Decoders, precharge, row/column architecture

A memory array is organized in rows and columns. A row decoder selects one word line from $2^n$ based on $n$ address bits. Column decoders/multiplexers select which bit lines to read or write. Precharge circuits reset bit lines to a midpoint or high before each access.

Security tie-ins. SRAM cells, on power-up, randomly settle to 0 or 1 based on tiny manufacturing mismatches. This randomness is unique per chip, and is the basis of SRAM PUFs: a chip's identity = the pattern of its SRAM cells at startup. Cold-boot attacks exploit the fact that DRAM cells retain their charge for seconds (longer when frozen), letting attackers read crypto keys from a powered-down machine. RowHammer exploits crosstalk between adjacent DRAM rows: hammering one row repeatedly induces bit flips in neighboring rows.