13. Programmable Logic: CPLD and FPGA // VLSI Design // bhaswanth

Not every project can afford a custom ASIC. Programmable logic delivers gate-level configurability at a fraction of the upfront cost.

13.1 CPLDs

A Complex Programmable Logic Device is an early form: a small array of macrocells (each macrocell is an AND-OR plane plus a flip-flop) connected by a global interconnect. CPLDs have non-volatile configuration (flash inside the chip), are small (hundreds to thousands of macrocells), and have predictable timing. Used for glue logic, level shifters, sequencers. Examples: Xilinx CoolRunner, Altera MAX series, Lattice MachXO (which is technically more FPGA-like).

13.2 FPGA architecture

A Field Programmable Gate Array is the modern programmable workhorse. The architecture:

plaintext

   ┌─────────────────────────────────────┐
   │ I/O blocks all around the perimeter │
   │ ┌──┬──┬──┬──┬──┬──┬──┬──┐           │
   │ │L │L │L │BR│L │D │L │L │           │
   │ ├──┼──┼──┼──┼──┼──┼──┼──┤           │
   │ │L │L │BR│L │L │L │L │L │           │
   │ ├──┼──┼──┼──┼──┼──┼──┼──┤           │
   │ │L │D │L │L │L │L │BR│L │           │
   │ ├──┼──┼──┼──┼──┼──┼──┼──┤           │
   │ │L │L │L │L │L │L │L │L │           │
   │ └──┴──┴──┴──┴──┴──┴──┴──┘           │
   │  L = Logic block (LUT+FF)           │
   │  BR = Block RAM                     │
   │  D = DSP slice (multiplier+adder)   │
   └─────────────────────────────────────┘

Each logic block typically contains:

Lookup tables (LUTs), usually 4-input or 6-input, where any 4- or 6-input boolean function is stored as a 16- or 64-bit truth table in SRAM cells. The LUT is the configurable gate.
Flip-flops for sequential logic.
A carry chain for fast adders.
Local muxes for stitching LUTs together.

The routing fabric connects logic blocks via switch matrices: SRAM-controlled pass transistors that connect or disconnect signal segments. Most of an FPGA's silicon is routing, not logic.

Specialized hard blocks alongside the soft fabric:

Block RAMs (BRAMs): small dedicated SRAMs (~36 kbits each, hundreds per chip).
DSP slices: hardware multiply-accumulate units (e.g., 25x18-bit MACs).
Clock managers / PLLs: clean, multiply, divide, phase-shift incoming clocks.
High-speed serial transceivers (SerDes): PCIe, 10/40/100 G Ethernet, JESD204B.
Hard CPU cores: ARM Cortex-A in Xilinx Zynq, MicroBlaze in older Xilinx, RISC-V cores in some Lattice/Achronix devices.

13.3 FPGA design flow

rendering diagram...

13.4 SRAM-based vs flash-based vs antifuse FPGAs

SRAM-based: configuration in volatile SRAM, reloaded from external flash at power-up. Most common (Xilinx/AMD, Intel/Altera, Lattice ECP5). Instantly reprogrammable but bitstream interception is a real attack.
Flash-based: on-chip flash configuration (Microchip PolarFire, Lattice MachXO3). Instant-on, lower power, more secure.
Antifuse: one-time programmable, used in rad-hard space FPGAs (Microchip RTAX).

13.5 FPGA security

Bitstream encryption: AES-256 on the bitstream is standard on every modern FPGA. Keys are stored in eFuses or battery-backed RAM.
Bitstream authentication: HMAC-SHA256 prevents bitstream tampering.
Anti-tamper sensors: voltage glitch, temperature, light detectors.
PUF on the FPGA: a hardware-unique key that even the user cannot read.

A bitstream is not the original Verilog. Reverse engineering the bitstream (Project IceStorm for Lattice iCE40, Project Trellis for Lattice ECP5, Project X-Ray for Xilinx 7-series) is an active research area, both for academic open-toolchain reasons and for security research.

13.6 FPGA in the wild

Network routers and SmartNICs (Xilinx Virtex/Versal). Microsecond-latency HFT engines. Edge AI (Microsoft Brainwave, AWS F1). Aerospace/defense (Microchip RTG4, PolarFire SoC). ASIC prototyping platforms (Palladium, ZeBu) emulate full chips before tape-out.