8. Layout Design // VLSI Design // bhaswanth

Layout is where Verilog meets glass. A layout is a stack of polygons on labeled layers, defining where every transistor, contact, wire, and via sits.

8.1 The layer stack

Modern processes have 30 to 80 mask layers, but conceptually they group as:

n-well: defines regions where PMOS will be built (in a p-substrate process).
p-well: where NMOS will be built (often the substrate itself, but explicit in twin-well processes).
Active (diffusion, OD): openings in the field oxide where the silicon surface is exposed to become source/drain regions.
Polysilicon (poly, GT): the gate material. Wherever poly crosses active, a transistor is formed.
N+ implant: makes the active regions of NMOS into n-type.
P+ implant: makes the active regions of PMOS into p-type.
Contact (CO): vertical hole filled with tungsten, connecting silicon or poly to Metal 1.
Metal 1 (M1): lowest interconnect layer.
Via 1 (V1): connection between M1 and M2.
Metal 2 (M2), V2, M3, V3, ... up to M12 or higher.

8.2 Stick diagrams

Before drawing actual polygons, designers sketch stick diagrams: schematic-like drawings where:

Green sticks = diffusion (active).
Red sticks = polysilicon (gates).
Blue sticks = metal 1.
Black sticks = metal 2.
Crosses or dots = contacts/vias.

A poly stick crossing a diffusion stick creates a transistor at the intersection. Stick diagrams are about topology, not dimensions. They let you plan the wiring before committing to design rules.

plaintext

   Stick diagram of CMOS inverter
 
      V_DD
       |
       |======== P-active ===
        \      |
         \     |
   in ----R---R---R-----     R = poly (red)
         /     |
        /      |
       |======== N-active ===
       |
      GND
                |
                |==== M1 ====  out

8.3 Design rules

Design rules are the geometric constraints the foundry imposes: minimum widths, minimum spacings, overlaps, exclusion zones. Originally expressed in lambda ( $\lambda$ ) units, where $\lambda$ was about half of the minimum feature size, so a rule like "minimum poly width = 2 $\lambda$ " was scalable across nodes.

Modern processes have hundreds of complex, non-scalable rules, including:

Minimum metal width and spacing per layer.
End-of-line extension rules.
Parallel-run length rules (longer parallel runs require wider spacing).
Density rules (each layer must be 30 to 70 percent filled in any window).
Pattern-dependent rules: certain patterns (like long parallel poly) require extra margin because of lithography stress.
Antenna rules: limits on the area of metal connected to a gate before being tied to diffusion (to prevent plasma-charge damage during fab).

You don't memorize these. The design-rule check (DRC) tool runs over your layout and flags violations. The layout-vs-schematic (LVS) tool verifies the layout matches the schematic.

8.4 Layout of CMOS NAND2

A 2-input NAND gate has two PMOS in parallel in the pull-up and two NMOS in series in the pull-down. Why? When either input is low, the output should be high → at least one PMOS must conduct → so PMOS in parallel. When both inputs are high, the output should be low → both NMOS must conduct → so NMOS in series.

plaintext

   NAND2 layout (top view, simplified)
 
   V_DD =====================
    |   |               |   |
    |  [P-active     P-active]
    |   |               |   |
   --- a (poly) -------------
    |   |    common drain    |
    |   |               |   |
   --- b (poly) -------------
    |   |               |   |
    |  [N-active]       |   |
    |   |               |   |
   GND ====================

Both PMOS share a source on $V_{DD}$ and dump their drains into the output node. Both NMOS sit in a column, the top one's drain at output, the middle node connecting them, and the bottom one's source at GND. This is the canonical "two-rail" cell layout used in standard-cell libraries.

8.5 Layout of CMOS NOR2

NOR2 is the dual: PMOS in series, NMOS in parallel. Same idea, swapped. NOR has slower pull-up than NAND because two PMOS in series fight against the lower hole mobility, so most synthesis tools prefer NAND for combinational logic.

8.6 Standard cells

A modern digital chip is built from a standard cell library: pre-designed, pre-characterized layouts of NAND, NOR, AND-OR-INVERT (AOI), inverters of various drive strengths, flip-flops, multiplexers, and so on. Each cell is the same height (so they tile in rows). The synthesis tool picks cells from the library; the place-and-route tool tiles them into rows and runs wires between them.

plaintext

   Standard cell row (top view)
   ┌───────┬─────────┬─────┬───────┬──────┐
   │ INV_X1│ NAND2_X2│ DFF │ NOR3_X1│ ...  │
   └───────┴─────────┴─────┴───────┴──────┘
     V_DD rail across the top (M1 strap)
     GND rail across the bottom (M1 strap)

Hand layout still happens for analog, RF, memory bit cells, standard cells themselves, and clock-tree leaves. Everything else is automated.

8.7 GDS-II and OASIS

When layout is done, the data is exported as GDS-II (the legacy industry standard) or OASIS (newer, more compact). These files describe every polygon, its layer, and any text labels. They are sent to the mask shop (often a separate company), which uses an e-beam writer to draw the patterns onto chrome-on-glass photomasks. A modern mask set has 80+ masks; a single critical mask costs $200K to$ 400K.

Security tie-in. The GDS-II file is the "source code" of a chip in a sense: anyone with it can build the chip. Theft of GDS-II files is the worst-case IP-leak scenario in semiconductor companies. End-to-end encryption, secure design environments, and per-engineer access controls protect the GDS pipeline.