4. MOSFET Physics for VLSI // VLSI Design // bhaswanth

We need to revisit the MOSFET equations from Chapter 1 with VLSI eyes, because the equations dictate the layout decisions.

4.1 The current equations

A long-channel NMOS transistor with gate-source voltage $V_{GS}$ and drain-source voltage $V_{DS}$ has three regions of operation:

Cutoff: $V_{GS} < V_{th}$ . Channel is not formed; ideally $I_{DS} = 0$ . (Real devices show subthreshold leakage.)

Linear (triode) region: $V_{GS} > V_{th}$ and $V_{DS} < V_{GS} - V_{th}$ .

$I_{DS} = \mu_n C_{ox} \frac{W}{L} \left[(V_{GS} - V_{th})V_{DS} - \frac{V_{DS}^2}{2}\right]$

Saturation region: $V_{GS} > V_{th}$ and $V_{DS} \geq V_{GS} - V_{th}$ .

$I_{DS} = \frac{1}{2} \mu_n C_{ox} \frac{W}{L} (V_{GS} - V_{th})^2 (1 + \lambda V_{DS})$

where $\mu_n$ is electron mobility, $C_{ox} = \varepsilon_{ox}/t_{ox}$ is gate-oxide capacitance per unit area, $W$ is channel width, $L$ is channel length, and $\lambda$ is the channel-length modulation parameter (the residual slope of $I_{DS}$ in saturation).

For digital logic we mostly care that:

A transistor with $V_{GS} = V_{DD}$ delivers a current that scales with $W/L$ . Bigger W (or smaller L) means stronger drive. This is how you size a buffer to drive a heavy load: copy and paste fingers of the transistor in parallel.
A transistor with $V_{GS} = 0$ is nominally off, but in modern processes leaks a measurable current.
The PMOS for a given W/L drives less current than NMOS (hole mobility is 2 to 3x lower). To balance an inverter, designers typically make PMOS 2 to 2.5x wider than the NMOS.

4.2 Body effect

The MOSFET has a fourth terminal, the body (sometimes "bulk"). When the source is tied to the body, $V_{th}$ is at its nominal value $V_{th0}$ . When the source is not at the same potential as the body, the threshold rises:

$V_{th} = V_{th0} + \gamma \left(\sqrt{2\phi_F + V_{SB}} - \sqrt{2\phi_F}\right)$

where $\gamma$ is the body-effect coefficient, $\phi_F$ is the bulk Fermi potential, and $V_{SB}$ is the source-to-body voltage. This matters whenever you stack transistors (as in a NAND gate's pull-down network), because the upper transistor sees its source above the body. Body effect makes stacked-NMOS gates slower than non-stacked ones, and is why some designers add body biasing circuits to deliberately tune $V_{th}$ at runtime.

4.3 Channel-length modulation

The $(1 + \lambda V_{DS})$ term in the saturation current means $I_{DS}$ doesn't really saturate flat; it slopes upward with $V_{DS}$ . This is because higher $V_{DS}$ shrinks the effective channel by extending the pinch-off region. Channel-length modulation reduces the output resistance of the transistor in saturation, which is bad for analog (gain falls) but mostly irrelevant for digital.

4.4 Multi- $V_{th}$ libraries

Modern foundries offer the same logic gate in multiple flavors:

HVT (high $V_{th}$ ): slow but very low leakage.
SVT (standard): balanced.
LVT (low $V_{th}$ ): fast but leaky.
Sometimes ULVT (ultra low) for bleeding-edge speed at huge leakage cost.

Different threshold voltages are made by varying the channel doping during implantation (and at modern nodes, by varying the gate-metal work function). The synthesis and place-and-route tools mix these to meet timing on critical paths while keeping non-critical paths at HVT for low leakage. A typical SoC ends up with most cells as HVT and a small percentage as LVT/ULVT on the slow paths.

4.5 Subthreshold leakage

Below threshold, the current does not jump to zero. It falls exponentially:

$I_{DS, \text{sub}} \approx I_0 \cdot e^{(V_{GS} - V_{th})/(n V_T)}$

where $V_T = kT/q \approx 26$ mV at room temperature and $n$ is a non-ideality factor around 1 to 1.5. This is the leakage that dominates standby power on advanced nodes. At 7 nm and below, leakage power can equal or exceed dynamic power.

4.6 FinFET and Gate-All-Around

Below 22 nm, the planar MOSFET stops working well: short-channel effects (DIBL, punch-through) ruin the off-state, and dopant fluctuations in the channel cause unacceptable $V_{th}$ variation. The fix is to wrap the gate around three sides (or all four) of a thin silicon "fin," getting much better electrostatic control.

plaintext

   Planar MOSFET (cross-section)
   ┌──────────────────┐
   │      Gate        │
   ├──────────────────┤  <- gate oxide
   │  channel under   │
   │ the gate (planar)│
   ├─────n+──n+──────┤
   └──────────────────┘
 
   FinFET (3D view)
        Gate (wraps the fin)
       ┌──────┐
       │ ┌──┐ │
       │ │Fin│ │     <- thin Si fin protruding up
       │ └──┘ │
       └──────┘
   The fin is the channel; the gate
   surrounds three sides of it.

FinFETs were introduced at Intel's 22 nm node in 2011 and have been the standard ever since. Below 3 nm, even FinFETs run out, and the industry is moving to Gate-All-Around (GAA) "nanosheet" transistors where horizontal sheets of silicon are surrounded on all four sides by the gate. Samsung shipped 3 nm GAA in 2022. TSMC is moving to GAA at the N2 node. Intel's "RibbonFET" is the same idea.

4.7 What "5 nm" means now (and doesn't mean)

Old process names referred to a real physical dimension, the gate length. At 22 nm and below the names became marketing labels rather than physical measurements. TSMC's "N5" has gate lengths around 18 to 22 nm, fin widths around 5 to 7 nm, and contacted gate pitches of 51 nm. Samsung's "5LPE" is comparable but not identical. Intel renamed its "10 nm Enhanced SuperFin" to "Intel 7" to make the comparison fairer. The number is now an indicator of roughly which generation the process belongs to, with density and performance specs that you must look up separately.