3. nMOS, pMOS, CMOS: Three Technologies, One Winner // VLSI Design // bhaswanth

Phase 2 of this curriculum introduced the MOSFET as a four-terminal device that turns on when the gate-to-source voltage exceeds a threshold. In VLSI we have to choose how to combine MOSFETs into logic.

3.1 nMOS-only logic

In the late 1970s, nMOS was the dominant logic family. A typical nMOS gate has an NMOS transistor as the pull-down network and either a resistor or a depletion-mode NMOS transistor as the pull-up load.

plaintext

       V_DD
        |
      [load: depletion NMOS or resistor]
        |
   in ──[NMOS]── out
        |
       GND

When input is high, the NMOS turns on and pulls the output low. When input is low, the NMOS is off and the load pulls the output high. The problem is that while the input is high, current flows continuously from $V_{DD}$ through the load through the NMOS to GND. This is called ratio-ed logic because the low output voltage $V_{OL}$ is set by the resistance ratio of pull-up to pull-down.

A typical pull-up to pull-down resistance ratio of 4:1 keeps $V_{OL}$ low enough to be read as a logical 0 by the next stage. But every nMOS gate that holds a low output is burning DC power, and you get lots of nMOS gates per chip. Power densities became unbearable around the LSI boundary. nMOS made the 6502, the Z80, and the original 8086, but the writing was on the wall.

3.2 pMOS-only logic

The mirror image of nMOS, with PMOS pull-down and PMOS pull-up. Slower because hole mobility in PMOS is about 2 to 3 times lower than electron mobility in NMOS. Was used in some early calculators and the 4004, then abandoned.

3.3 CMOS: complementary symmetry, the winner

Complementary MOS uses a pull-up network of PMOS transistors and a pull-down network of NMOS transistors, arranged so that for any input, exactly one of the two networks is conducting and the other is off.

For the inverter:

plaintext

        V_DD
         |
       [PMOS]      <- pull-up
         |
   in ───┤
         |
       [NMOS]      <- pull-down
         |
        GND
                    out is taken from the middle node

When input is low: the PMOS is on (gate-to-source is $-V_{DD}$ , well below $V_{tp}$ ), the NMOS is off. Output is pulled to $V_{DD}$ . Critically, NMOS is off, so there is no DC current path from $V_{DD}$ to GND.

When input is high: NMOS on, PMOS off. Output is pulled to GND. Again, PMOS is off, no DC current path.

DC power is essentially zero (just leakage). All the power goes into charging and discharging the output capacitance during transitions. This is why CMOS won. A chip with a billion gates, switching at typical activity factors, dissipates a few tens of watts. The same chip in nMOS would dissipate kilowatts.

3.4 The bigger picture

CMOS's victory is one of the cleanest examples in engineering of a "second-order" design choice that ate everything. The transistors themselves are not necessarily "better." The series complementary structure that you only get with both flavors available is what saves the power. From the Pentium to the M4 Max, every commercial digital chip is essentially a vast tree of CMOS gates.