We started at a circle of pure silicon pulled from a melt and ended at a side-channel attack on AES running in 7 nm CMOS. Along the way:
- The CMOS inverter as the atomic operation of digital logic, with derived delay, dynamic power, and noise margins.
- The fab flow from sand to wafer to lithography to etch to implant to metallization to packaging.
- Scaling, both Dennard's free lunch and the post-2005 "every gain hurts something" reality.
- Layout (stick diagrams, design rules, GDS-II), logic styles beyond static CMOS, memory (6T SRAM, 1T1C DRAM), and flip-flops built from transmission gates.
- FPGAs as the user-programmable cousin of the ASIC.
- Low-power techniques (clock gating, power gating, multi-Vth, multi-Vdd, DVFS, body bias) and DFT (scan, BIST, JTAG).
- Hardware-security ties at every step: side channels, glitch attacks, decap, PUFs, Trojans, anti-tamper, and the EUV supply-chain choke point.
Chapter 17 drills into embedded peripherals and protocols (UART, SPI, I2C, USB, CAN). Chapter 24 picks up the security thread for its dedicated treatment. Every layer of metal, every transistor's leakage, every flop's setup time will reappear there as either an attack surface or a defensive measure.
When someone says "5 nm" or "FinFET" or "scan chain" or "EUV," you should be able to draw the cross-section, write the equations, and explain the security implications. Welcome to VLSI.