Designing the chip is half the job. Verifying it works is the other half. On large projects the verification team is often bigger than the design team.
- Functional simulation: run the RTL in a simulator (VCS, Xcelium, Verilator).
- Constrained-random verification: generate random stimulus obeying protocol constraints; collect functional coverage.
- Formal verification: prove properties with SAT/SMT solvers. Powerful for control logic.
- Emulation: run the design on a giant FPGA emulator (Cadence Palladium, Synopsys ZeBu) at megahertz speeds. Lets you boot real software pre-silicon.
- Static timing analysis (STA): every path's setup/hold under worst-case PVT.
- Power, signal-integrity (crosstalk, IR drop, electromigration), and logic-equivalence checks between RTL, synthesis, and post-route netlists.
- Post-silicon validation: test the actual fabricated chip with bring-up software.