2. The Fabrication Recipe

If you want to understand anything about hardware security at the deep end, decapsulation, fault injection, hardware Trojans, anti-tamper meshes, you need to understand how a chip is actually made. The whole modern flow is roughly the same regardless of node, but the cleanroom is so quiet and so expensive that it might as well be magic. Let's open the box.

2.1 From sand to a 300 mm boule

Silicon is the second most abundant element in the Earth's crust, after oxygen, and most of it shows up bonded to oxygen as silica (sand, quartz). To make a chip-grade wafer we need silicon that is eleven nines pure, 99.999999999 percent. Getting there involves:

1. Reduction. Sand is heated with carbon in an electric arc furnace to make metallurgical-grade silicon (MGS), about 98 percent pure. Already useful for solar cells, useless for chips.
2. Conversion to trichlorosilane. MGS reacts with HCl to make SiHCl3, a liquid that can be distilled.
3. Distillation and Siemens process. SiHCl3 is repeatedly distilled to ultra purity, then thermally decomposed onto a hot silicon rod in a bell jar. The rod grows into a polycrystalline ingot of electronic-grade silicon (EGS).
4. Czochralski crystal growth. EGS chunks are melted in a quartz crucible. A small "seed crystal" of perfect single-crystal silicon is dipped into the melt and slowly pulled upward while rotating. As silicon cools onto the seed, it adopts the seed's crystal lattice. The result is a giant cylindrical boule of single-crystal silicon, today 300 mm in diameter and a meter or two long, weighing hundreds of kilos.

The Czochralski step is much like dipping a thread into honey and pulling it up so that honey strings off, except you are pulling a meter-long telephone-pole crystal of pure silicon, in a vacuum or argon atmosphere, at temperatures near 1450°C, with rotation rates and pull speeds tuned to the millisecond.

        Pull rod
            |
            |
        [Seed crystal]
            |
           /|\
          / | \
         /  |  \   Growing single-crystal boule
        /   |   \
       |    |    |
       |    |    |
       |____|____|
       |~~~~|~~~~|   Molten silicon (1450°C)
       |~~~~|~~~~|
       =====Q=====   Quartz crucible, graphite heater

The boule is sliced with diamond wire saws into circular disks about 0.7 mm thick. Those are wafers. They are lapped, polished, etched, and re-polished to mirror smoothness. Atomic flatness on the working face is required because every step that follows depends on the wafer being flat to within a few nanometers across 300 mm of diameter, which is the same as asking a football field to be level to within the thickness of a hair.

Some specialized wafers are silicon-on-insulator (SOI) with a buried oxide layer, or epitaxial wafers with a controlled-doping epi layer grown on top. RF and high-voltage processes use these heavily.

2.2 The cleanroom: war on dust

Every wafer step happens in a cleanroom, classified by particles per cubic foot. A chip line runs in ISO Class 1 to Class 5: between 10 and 100,000 particles of 0.1 micron size or larger per cubic meter. The outdoor air you are breathing right now has on the order of 35 million particles per cubic meter. A single particle bigger than the feature size, landing on the wafer at the wrong moment, will kill the die it lands on.

Cleanrooms enforce this by laminar HEPA-filtered down-flow air, by moonsuit "bunny suits" worn by operators, and by air-locked entries. Modern fabs run almost entirely lights-out, with wafers moving in FOUPs (Front-Opening Unified Pods) on overhead rails between tools, untouched by humans for the entire 12-week production run.

Security tie-in. A counterfeit chip detector can sometimes spot fakes by looking for cleanroom-quality features that the counterfeiter could not reproduce. Reverse engineers and academic researchers run "dirty cleanrooms" at university labs which are good enough to do limited rework or selective decapsulation.

2.3 Oxidation: growing glass

The first chemical step on most processes is oxidation, growing a thin layer of silicon dioxide (SiO2, glass) on the wafer. Simply heating silicon to 1000°C in an oxygen atmosphere does it: the oxygen reacts with silicon at the surface, building up SiO2 atom layer by atom layer.

SiO2 plays many roles:

• A gate dielectric under the polysilicon gate of a MOSFET, separating the gate from the channel. Below 2 nm, the oxide leaks too much from quantum tunneling, which is why post-2007 nodes use high-k materials such as hafnium oxide (HfO2) instead.
• A mask during ion implantation: oxide blocks dopants from entering covered regions.
• An isolation between adjacent devices (LOCOS, then shallow trench isolation, STI).
• An insulator between metal layers (interlayer dielectric, ILD), although low-k materials replace pure SiO2 here at modern nodes.

2.4 Photolithography: the photographic printing press at the heart of the chip

This is the step that makes the entire industry tick, and the one that most directly determines what is the "smallest feature" we can build. Lithography projects a pattern from a glass-and-chrome photomask (also called a reticle) onto the wafer's surface, just like an enlarger projects a negative onto photographic paper. The wafer is coated with photoresist, a polymer that becomes either soluble or insoluble where light hits it.

The flow is a darkroom dance:

1. Spin-coat a thin film of photoresist (a few hundred nanometers thick).
2. Soft-bake to drive off solvents.
3. Expose through the reticle. UV light (or EUV) passes where the mask is clear, blocked where the mask is opaque.
4. Post-exposure bake to amplify chemistry.
5. Develop in a solvent. Soluble regions wash away. The remaining resist is now a stencil of the mask pattern.
6. Etch the underlying material wherever resist is not protecting it.
7. Strip the remaining resist.

    [UV/EUV light]
         |||||
   __ MASK __
  |o|o|o|o|o|o|        (clear areas)
  --------------
   \\\projection optics, 4x reduction//
   __________
   //photoresist//
   ============           <- wafer surface

The wavelength of the light matters because of diffraction: the smallest feature you can resolve is roughly $k_1 \lambda / NA$, where $\lambda$ is the wavelength and $NA$ is the numerical aperture of the optics, and $k_1$ is a process-dependent factor. The industry has worked obsessively to push every term:

• g-line mercury vapor (436 nm), then i-line (365 nm) drove early VLSI.
• KrF excimer laser (248 nm) carried the industry through the 1990s.
• ArF excimer (193 nm), with immersion lithography (water between lens and wafer to raise NA), drove 90 nm down to about 10 nm.
• Multi-patterning (LELE, SAQP) splits one critical layer into multiple masks to push beyond the wavelength limit. Cost rises sharply with each extra exposure.
• EUV lithography at 13.5 nm wavelength is the new frontier. EUV is generated by zapping tin droplets with a CO2 laser at 50,000 pulses per second, creating a plasma that emits 13.5 nm photons. A single ASML NXE:3600 EUV scanner costs about $200 million. ASML in the Netherlands is the only manufacturer in the world. TSMC, Samsung, Intel, and SK Hynix all bought from the same supplier.

Geopolitical and security note. The EUV monopoly is a single point of supply-chain failure. US export controls deny EUV machines to China. This is the most consequential hardware-supply-chain story of the 2020s. Anything you read about "decoupling" or "chip independence" is downstream of it.

2.5 Etching and stripping

After lithography you have resist patterns on the wafer. To turn those patterns into actual structures, you etch the material the resist is sitting on. Two flavors:

• Wet etching uses liquid acids or bases. Cheap, fast, but isotropic (eats sideways under the resist as well as down). Useful for non-critical layers.
• Dry etching, almost always reactive ion etching (RIE), uses a plasma of reactive gases in a vacuum chamber, with an electric field accelerating ions vertically into the wafer. This produces highly anisotropic (vertical) sidewalls, essential for tight features.

After etching, the remaining photoresist is "stripped" with oxygen plasma or solvent. The wafer is cleaned, often with the legendary RCA clean (a sequence of H2SO4/H2O2 and NH4OH/HCl mixtures) that removes organic and metallic contamination.

2.6 Doping by ion implantation

Recall from Chapter 1 that an n-type silicon region has extra electrons (donor atoms like phosphorus or arsenic), and a p-type region has missing electrons (acceptor atoms like boron). To make a transistor we need precisely placed n-type and p-type regions inside the silicon.

The modern way to do this is ion implantation: ionize the dopant gas, accelerate the ions to tens or hundreds of keV in an electric field, and bombard the wafer. Each ion punches a few hundred angstroms into the silicon and stops, lodged in the lattice. The dose (atoms per cm^2) and the energy (depth) are tightly controlled.

After implantation, the wafer is annealed at high temperature to repair the lattice damage and to "activate" the dopants by diffusing them into substitutional lattice sites. Modern processes use millisecond laser anneals to limit thermal diffusion (so you can implant a sharp profile and keep it sharp).

2.7 Metallization: the wiring above the transistors

Once the transistors are built in the silicon, we have to wire them up. This is the back end of line (BEOL). A modern chip has 10 to 18 metal layers, each separated by inter-layer dielectric (ILD, low-k for low capacitance). Lower layers are thinner with finer pitch (for short signal nets), upper layers are thicker (for power delivery and long clocks).

Aluminum was the metal of the 1990s. Copper took over around the year 2000 because of its lower resistivity (1.7 µΩ·cm vs Al's 2.7) and better electromigration tolerance. Copper cannot be etched with plasma well, so the industry switched to a damascene process: etch trenches in the dielectric, deposit a copper barrier, electroplate copper, then chemical-mechanical polish (CMP) the surface flat. Vias between layers are made the same way (often "dual damascene" combining via and trench in one fill).

Picture the metal stack as a city of skyscrapers:

• Active transistors are the basement and ground floor.
• Metal 1 to Metal 4 are the lower commercial floors, with dense pedestrian traffic (short signal wires).
• Metal 5 to Metal 9 are the office floors with bigger hallways (block-level routing, long buses).
• Metal 10 and above are the rooftop (clock distribution, power grid, top-level signals).
• Vias are the elevators, connecting one floor to the next.

   M12 (thick)   ===========   power, long clock
   M11           ===========
   M10           ==========
    ...          ==========
   M3            ==========
   M2            ==========
   M1 (thin)     ==========   intra-cell wiring
   --- contacts ---
   [polysilicon gate]
   [active n+ / p+ regions]
   [silicon substrate]

2.8 Back end: dicing, packaging, test

When all layers are done, the wafer is wafer-tested at room and elevated temperature with a probe card that pokes pads on every die. Bad dies are inked. The wafer is then diced with a diamond saw or stealth laser into individual dies.

Packaging follows: wirebonding for lower-end packages (gold or aluminum wires connect die pads to package pins), or flip-chip for high-performance packages (the die is flipped and bonded directly to the package via solder bumps). Top-of-the-line packages are 2.5D with multiple dies on an interposer (HBM next to GPU on a silicon interposer) and 3D with stacked dies and through-silicon vias (TSVs).

After packaging, final test runs production patterns at multiple temperatures and voltages. Burn-in stresses parts at elevated temperature/voltage to weed out infant mortality.

2.9 The complete picture: a Mermaid flow

A 5 nm process visits hundreds of tools across 80+ photomasks, runs for 3 to 4 months of wafer-line time, and costs the foundry $100M+ in capital amortization per square millimeter of leading-edge silicon over the life of the part. Mask sets alone cost$50M to $100M for an advanced node. This is why the fabless model dominates: most companies (Apple, AMD, NVIDIA, Qualcomm, Broadcom) only design chips, then pay TSMC or Samsung to fabricate them. Only Intel, Samsung, and TSMC continue to operate leading-edge fabs.