11. Sequential Elements // VLSI Design // bhaswanth

The flip-flops we wrote behavioral Verilog for in Chapter 4 must be physically built. Standard-cell flip-flops are tiny circuits, ~20 to 30 transistors, of carefully arranged transmission gates and inverters.

11.1 The transmission-gate master-slave flip-flop

plaintext

   D ──[TG1]──*── inv ──*──[TG2]──*── inv ──── Q
              |  ^      |          |   ^
              |  loop   |          |   loop
              feedback  |          feedback
              (TG3)     |          (TG4)
                        clk-controlled

TG1 transparent when clk=0, captures D into the master latch.
TG3 closes the master's loop when clk=1 (holding the value).
TG2 transparent when clk=1, transfers master value to slave.
TG4 closes the slave's loop when clk=0.

So D is sampled on the rising edge of clk and appears on Q after a small delay.

11.2 Setup and hold time

For correct sampling:

Setup time $t_{su}$ : D must be stable for at least $t_{su}$ before the clock edge.
Hold time $t_h$ : D must remain stable for at least $t_h$ after the clock edge.

If either is violated, the flip-flop can enter metastability, where its output hovers at an undefined level for nanoseconds before resolving randomly to 0 or 1.

11.3 Maximum clock frequency, derived

For a path from flip-flop A through some combinational logic to flip-flop B:

$T_{clk} \geq t_{cq,A} + t_{logic,max} + t_{su,B} + t_{skew}$

where $t_{cq}$ is clock-to-Q delay and $t_{skew}$ is the worst-case skew between the clocks at A and B. Solving for the maximum frequency:

$f_{max} = \frac{1}{t_{cq} + t_{logic,max} + t_{su} + t_{skew}}$

The hold-time constraint is symmetric:

$t_{cq,A} + t_{logic,min} \geq t_{h,B} + t_{skew}$

If hold violates, no clock frequency saves you; the chip simply doesn't work. Hold violations are caught by the static timing analyzer (STA) and fixed by inserting buffers in short paths.

11.4 Sense-amp flip-flops

For very high-frequency designs, a sense-amplifier-based flip-flop uses two cross-coupled inverters that are differentially set by the input D and its complement, gated by the clock. They are faster than transmission-gate flops and have negative setup time (D can arrive after the clock edge by a tiny amount), at the cost of higher complexity.

11.5 Scan flip-flops

Every flip-flop in a digital chip is normally a scan flip-flop: a flip-flop with an extra mux on the D input, switching between a "functional" D and a "scan" S based on a scan-enable signal. In test mode, all flops are chained S→Q→S→Q into one giant shift register, so a tester can set or read every flop's state. We will return to scan in DFT below.

11.6 Verilog for flip-flop inference

Synthesis infers flip-flops from "always @(posedge clk)" blocks:

verilog

module reg32 (
    input         clk,
    input         rst_n,
    input  [31:0] d,
    output reg [31:0] q
);
    always @(posedge clk or negedge rst_n) begin
        if (!rst_n)
            q <= 32'b0;
        else
            q <= d;
    end
endmodule

Synthesis sees this and instantiates 32 D flip-flops with asynchronous active-low reset.

verilog

// 4-bit synchronous up counter
module counter4 (
    input        clk,
    input        rst,
    input        en,
    output reg [3:0] count
);
    always @(posedge clk) begin
        if (rst)        count <= 4'b0;
        else if (en)    count <= count + 1'b1;
    end
endmodule

This synthesizes to four DFFs with combinational increment + mux logic on their D inputs.