10. Logic Styles // VLSI Design // bhaswanth

Static CMOS is dominant but not the only way to build a gate. Several alternatives trade speed, power, and area in different ways.

10.1 Static CMOS (the default)

What we already covered. Pull-up complementary to pull-down, full rail-to-rail swing, no static current. Excellent noise margins. Slightly more transistors than other styles. Default for almost everything.

10.2 Pseudo-nMOS

A static CMOS gate with the entire PMOS pull-up replaced by a single always-on PMOS (gate tied to GND). Smaller than full CMOS but burns DC power when output is low (similar to nMOS-only logic). Used for occasional NOR-heavy decoders, although static CMOS has won here too.

10.3 Ratio-ed logic

Any logic family where the low (or high) output level depends on a ratio of pull-up to pull-down strengths. nMOS is one example. Pseudo-nMOS is another.

10.4 Pass-transistor logic and transmission gates

Use transistors as switches rather than as pull-up/pull-down devices. A pass transistor lets a signal through when its gate is on. NMOS pass transistors lose a $V_{th}$ on a high-going signal (because NMOS turns off when source approaches gate); PMOS lose a $V_{th}$ on a low-going one.

A transmission gate is an NMOS in parallel with a PMOS, with complementary gate signals. It passes both rails cleanly. Transmission gates are the workhorses of multiplexers, latches, and flip-flops in standard-cell libraries.

plaintext

   Transmission gate
       NMOS
   ────[N]────
        |
   en ──┤
        |
   ────[P]────   (PMOS, gate driven by NOT en)
       PMOS

10.5 Dynamic logic: domino, NORA

Dynamic logic uses a clocked precharge and evaluate. During the precharge phase, a PMOS pulls the output node high; during the evaluate phase, an NMOS pull-down network conditionally discharges it.

Domino logic:

plaintext

   clk ──[PMOS precharge]── V_DD
                |
                * <- output node (precharged high)
                |
              [NMOS pull-down network: a, b, c, ...]
                |
   clk ──[NMOS evaluate]── GND

When clk is low, output is precharged high. When clk goes high, the evaluate NMOS turns on and the network discharges if its inputs allow.

Dynamic logic is fast and compact but has noise problems (the precharged node is a high-impedance node, vulnerable to crosstalk and leakage), and it does not work well with low frequencies (precharge can leak away). It enjoyed brief popularity in the late 1990s in high-speed CPUs (notably Intel's NetBurst Pentium 4 used self-timed domino in many places). Modern designs use it sparingly because it complicates everything (testability, low-power, leakage).

NORA (NO-Race) logic alternates n-type and p-type domino blocks to remove the need for inverters between stages.

10.6 What do you actually use?

For 99 percent of digital logic on modern chips: static CMOS, with transmission-gate multiplexers in flip-flops and latches. Dynamic logic survives in tiny pockets (CAMs, very fast adders).