The security-relevant phenomena that fall out of physical chip design.
18.1 Side channels born in CMOS
Every CMOS transition burns joules. Multiply across billions of gates and the chip's power becomes data-dependent. Differential Power Analysis (DPA) measures this across many crypto operations and recovers the key. Simple Power Analysis (SPA) reads single traces. EM emanations (the chip is an antenna of switching currents) is the same channel through a different sensor. Mitigations live at the cell-library level: dual-rail logic (WDDL), masking schemes, balanced gates, on-chip regulators that flatten the power signature.
18.2 Glitch and fault attacks
A drop or clock glitch violates setup time on a critical flop, forcing it to capture a wrong value. Attackers use this to skip a wrong-PIN comparison, bypass a signature check, or leak a key. Mitigations: redundant computation, dual-rail logic, voltage/clock monitors, time-triggered double execution.
18.3 Decapsulation and reverse engineering
Fuming nitric acid removes the plastic package; FIB polishes layer by layer; SEM imaging digitizes each layer; software stitches them into a netlist. TechInsights does this commercially for competitive analysis. The same techniques in attacker hands enable IP theft and counterfeit creation. Defenses: camouflaged gates (function depends on a sub-resolution feature), active metal-mesh shields, logic locking (function depends on a secret key), split manufacturing (front-end at one fab, back-end at another).
18.4 Fault injection at the silicon level
Laser fault injection uses a focused 1064 nm pulse on an exposed die to flip flops. Electromagnetic fault injection (EMFI) does similar without decapping. Body-bias attacks drive the substrate to inject errors. Defenses combine sensors (light, voltage, temperature) and hardened circuit styles.
18.5 PUFs
Physically Unclonable Functions turn manufacturing variation into a per-chip secret:
- SRAM PUF: power-up state of each cell is random but stable for a given die.
- Ring-oscillator PUF: identical ROs run at slightly different frequencies; comparisons yield bits.
- Arbiter PUF: two nominally identical paths race; the winner is path-dependent.
PUFs sit at the heart of modern IoT secure-element keys, smartcards, and FPGA security cores. The manufacturer cannot read the key.
18.6 Hardware Trojans
A malicious modification at the IP, EDA, or fab stage that activates under rare conditions to leak secrets, disable function, or open a backdoor. Detection: side-channel fingerprinting, post-fab imaging, split manufacturing. A Trojan can be a single extra gate among billions; this is one of the hardest open problems in hardware security.
18.7 Anti-tamper
High-value chips (smartcards, HSMs, Apple's Secure Enclave, Google Titan) include active metal-mesh shields, voltage/temperature/frequency monitors that wipe keys on anomaly, photodetectors that fire on decapsulation, and clock-frequency randomization to obscure timing side channels.
18.8 Supply-chain risk and EUV
The single-source EUV supply chain is itself a security concern. Whoever controls the one ASML factory in Veldhoven controls who can manufacture leading-edge chips. The geopolitics of chips is the geopolitics of national power.