6. Latch-up: the Parasitic SCR That Kills Chips // VLSI Design // bhaswanth

A CMOS chip has both n-type and p-type regions in the same substrate. That arrangement, by accident, builds a four-layer PNPN structure that is electrically a silicon-controlled rectifier (SCR). Under normal operation it does nothing. But if any node briefly overshoots past $V_{DD}$ or undershoots below GND, the SCR can trigger, conducting a huge current from $V_{DD}$ to GND through the substrate, until the chip is power-cycled (or destroyed by heat).

plaintext

     V_DD                       GND
       |                         |
    [P-tap]   [PMOS]   [NMOS] [N-tap]
       |        |         |     |
       n+   p+   n+   p+   n+
       \____n-well____/   p-substrate
              |               |
   parasitic vertical PNP    parasitic lateral NPN
              \_  positive feedback _/

The parasitic PNP (P-source / n-well / p-substrate) and parasitic NPN (n-source / p-substrate / n-well) form a regenerative pair. Once triggered, $I_{NPN}$ feeds the base of PNP and vice versa, locking them on.

Mitigations:

Guard rings: heavily doped substrate contacts that "soak up" stray currents before they can trigger the SCR. Place guard rings around analog blocks, near I/O, and around sensitive RAMs.
Heavy substrate doping lowers the resistance of the substrate, raising the trigger threshold.
Epitaxial wafers on heavily-doped substrate are common in CMOS for this reason.
ESD-protection circuits with good clamping prevent overshoots in the first place.
Layout rules mandate minimum spacing from n-well to n+ source, and require well/substrate taps at frequent intervals.

Security tie-in. Latch-up can be deliberately induced by fault-injection attackers: a sharp $V_{DD}$ glitch can trigger latch-up in an unprotected chip, freezing logic and possibly bypassing security checks. Smartcards in particular are heavily hardened against this attack.